Micron has unveiled its memory roadmap for the coming years: DDR6 for servers with roughly double the bandwidth of DDR5, LPDDR6 with more than 35% better power efficiency, HBM memory stacked directly on the compute chip by around 2028, and a G11 NAND with more than 400 layers. The company detailed the plans in a presentation on its multi-generation DRAM, HBM, and NAND strategy, reported by Wccftech on October 21, 2026.
Micron’s memory roadmap in 20 seconds
- DDR6 will double DDR5’s bandwidth and will be built on the 1δ node.
- LPDDR6 improves efficiency by more than 35%, and Micron is developing it with Meta.
- vHBM, memory stacked on the chip, will arrive around 2028.
- G11 NAND will pass 400 layers in 2027.
The announcement comes amid a memory shortage driven by AI demand, which has turned DRAM and HBM into a bottleneck for data centers. Micron says agentic AI has multiplied memory demand 30x compared with traditional inference. To understand where things are headed, it helps to see where each memory type comes from.
From DDR5 to DDR6: Server Memory
Main memory for PCs and servers has doubled its speed generation after generation. JEDEC, the industry’s standards body, published the DDR5 spec in 2020, and it’s the foundation of today’s servers. Micron already makes 512 GB DDR5 modules, and the next step on its roadmap is a 1 TB RDIMM.
DDR6 will be the successor. Micron describes it as offering roughly double DDR5’s bandwidth, aimed at servers that need high reliability, and the company wants to be a lead partner for its biggest customers as they adopt it. It hasn’t given speeds or a firm date: it’s positioned as next-generation and will be built on the 1δ (1-delta) node. According to earlier reporting picked up by Wccftech, Samsung, SK hynix, and Micron are all aiming to commercialize it between 2028 and 2029.
That 1δ node is the other key piece. Micron says it will improve bit density by roughly 25% over the previous node, with ramp-up expected in the second half of 2027. The company notes DRAM has multiplied bits per wafer 400x since 1995 across 22 nodes, and has confirmed it will stick with 6F² cells rather than jump to 4F², citing complexity and cost — as CloudNews reported when Micron called 4F² DRAM a myth while YMTC and CXMT race ahead with it. 3D DRAM will come later, after products using High-NA EUV lithography.
LPDDR6 Moves From Mobile Into the Data Center
Low-power memory, originally built for phones, has found a place in AI servers. JEDEC published the LPDDR6 standard (JESD209-6) in July 2025, with speeds between 10,667 and 14,400 MT/s and 24-bit channels split into two 12-bit subchannels, according to Notebookcheck. Micron says its LPDDR6 delivers more than 35% better power efficiency than LPDDR5 and is positioning it for both mobile and data centers. It’s working with Meta on using it in future data centers. On the consumer side, CloudNews reported how CXMT is speeding up with LPDDR6, and Xiaomi will debut it in its next foldable.
HBM: From Stacks Beside the Chip to Vertical Memory
HBM (High Bandwidth Memory) stacks several DRAM chips and places them next to the GPU to deliver enormous bandwidth. It’s the memory that defines today’s AI accelerators. On Micron’s timeline, 8-layer HBM3E entered volume production in 2024, and the 12-layer version shipped in 2025. HBM4, whose JEDEC standard (JESD270-4) was published in 2025, arrives this year in 12-layer, 36 GB versions, with 2.8 TB/s per stack according to Micron. HBM4E is already sampling with key customers, and the company places HBM5 around 2028, HBM5E around 2029, and HBM6 around 2030.
The big new idea is vHBM, or 3D vertical HBM. Instead of placing memory beside the processor, it’s stacked directly on top of the compute chip, with the shortest possible path between the two. Micron says this improves bandwidth per watt and tokens per watt on AI workloads. vHBM1 would arrive around 2028 and vHBM3 around 2030, and it depends on technologies like hybrid copper bonding, integrated heat sinks, and thermally aware design. Micron is also preparing vEIM, a vertical memory for edge inference, targeting about 2 TB/s per module. CloudNews recently explained how SK hynix is validating HBM5 with TSMC ahead of the next AI generation, a similar bet.
NAND G11: More Than 400 Layers
In storage, 3D NAND has kept stacking layers to gain density. Micron is preparing G11, which will pass 400 layers thanks to wafer bonding, with volume ramp-up expected in the second half of 2027. Compared with its G9, the company promises roughly double the bit density, up to 1.5x faster I/O, and more than 25% less energy per data transfer. Beyond G11, it’s researching high-mobility materials and new cell architectures, plus NAND built specifically for AI. All these dates are Micron’s own projections.
Frequently Asked Questions
When will DDR6 memory arrive?
Micron hasn’t given a firm date. It’s positioned as next-generation, built on the 1δ node, and the industry is aiming to commercialize it between 2028 and 2029.
How much faster will DDR6 be than DDR5?
According to Micron, it will offer roughly double DDR5’s bandwidth.
What is vHBM?
It’s HBM memory stacked directly on the compute chip. Micron expects the first generation around 2028 and vHBM3 around 2030.
How many layers will Micron’s G11 NAND have?
More than 400, with volume production expected to begin in the second half of 2027.
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