Micron has ruled out bringing the 4F² DRAM memory cell into production, the architecture Samsung, SK hynix, and Chinese manufacturers CXMT and YMTC are counting on to keep shrinking memory. Its chief technology and product officer, Scott DeBoer, went as far as calling its density advantage a myth at a technical seminar held on October 21, 2026. Meanwhile, YMTC is working on a 4F² DRAM prototype at 9,600 MT/s, and CXMT is promising its first module with this technology before the end of the year.
The 4F² DRAM battle in 30 seconds
- Micron says it has researched the 4F² cell for more than 20 years and sees no viable path to scale it.
- It will instead keep extending the 6F² cell and later move to 3D DRAM.
- YMTC, known for its NAND, is developing a 4F² DRAM with a vertical-channel transistor targeting 9,600 MT/s.
- CXMT plans to launch a 4F²-based server DDR5 RDIMM module before year-end, with specs still undisclosed.
The disagreement matters. DRAM has found it increasingly hard for years to shrink its cells, and memory has become one of the bottlenecks for AI data centers. How and when each manufacturer manages to pack more density per wafer will shape costs and production capacity in the years ahead.
What the 4F² cell is and why it promises more density
In DRAM, each bit is stored in a cell made of a transistor and a capacitor. The measure F is the smallest feature size that can be manufactured in a given process. Today’s DRAM uses 6F² cells, where the transistor and capacitor sit side by side. In the 4F² architecture, the transistor is placed vertically (hence the name vertical-channel transistor, or VCT) with the capacitor stacked on top, so each cell occupies a 2F-by-2F square.
On paper, a 4F² cell takes up about two-thirds of the area of a 6F² cell at the same manufacturing node, which lets more bits fit on each wafer. The difficulty lies in manufacturing reliable, high-performance vertical transistors at scale. Samsung presented a 16Gb 4F² design at the 2026 ISSCC conference, though its initial target of mass production by 2028 no longer has a firm date, and SK hynix has described a 4F² platform with a vertical gate for a future node, according to Tom’s Hardware.
Micron rules out 4F² and bets on 3D DRAM
Micron is going a different way. At its technical seminar, the company explained it has spent more than 20 years researching the 4F² cell and doesn’t see a viable path to scale it. Scott DeBoer talked about fundamental scaling problems and compared its supposed density advantage over 6F² to something of a myth. According to DIGITIMES, Micron considers the architecture to deliver limited benefits in exchange for more cost and complexity.
Micron’s alternative is to stretch the 6F² cell across more generations and then jump to 3D DRAM, which stacks cells vertically the way NAND flash memory already does. According to information published after the seminar, its Boise, Idaho fab will start mass-producing 1-delta node DRAM in the second half of 2027, after the current 1-gamma node, and its first 3D architectures, called 3D1 and 3D2, would arrive in later generations, between the 1-zeta and 1-eta nodes. These are the company’s own plans, with no firm dates set for 3D DRAM.
YMTC and CXMT push ahead with 4F²
The Chinese manufacturers are headed in the opposite direction. YMTC, which has carved out a place among the big NAND players and is preparing to go public in Shanghai, wants to bring its Xtacking technology to DRAM. According to Counterpoint Research, cited by Wccftech, the company has been developing and testing a 16Gb LPDDR5 at 7,500 MT/s at its Fab 2 since October 2025, with output of around 5,000 wafers a month. The next version, at 9,600 MT/s, would use a 4F² cell with a vertical-channel transistor and would be mass-produced at its Fab 3, with no date announced. Revista Cloud already reported how YMTC is aiming to dethrone Samsung in enterprise NAND.
CXMT, China’s largest DRAM maker, is a step ahead on the calendar. Its chairman, Cao Kanyu, announced that its first 4F² product, a server DDR5 RDIMM module, will arrive before 2026 is out. The company calls its vertical transistor design Vertical Surrounded Gate, presented an 8Gb research array at the 2023 IEDM conference, and claims to hold more than 300 related patent families. It hasn’t disclosed speeds, capacities, or volumes, though, and South Korean media suggest its first products may use 4F² only partially. CXMT, which according to TrendForce reached 9.5% of global DRAM revenue in the second quarter, is one of the companies pushing China’s memory battle to a new level.
For Chinese manufacturers, 4F² has an added appeal: it lets them gain density without depending as much on shrinking the minimum feature size, a field where restrictions on exporting advanced lithography equipment limit them. That’s an argument raised by industry analysts; the companies themselves haven’t framed it that way in their announcements. Semiconductor expert Fred Chen, cited by Wccftech, argues that if CXMT solves the 4F² problems it could move from an effective 1c process to 1d.
Frequently asked questions
What is 4F² DRAM?
It’s a cell architecture where the transistor sits vertically beneath the capacitor, so each cell occupies about two-thirds of the area of today’s 6F² cell.
Why is Micron ruling out 4F²?
Micron says that after more than 20 years of research it sees no viable scaling path, and that its density advantage is limited compared to its cost. It prefers to extend 6F² and move to 3D DRAM.
What is YMTC preparing in DRAM?
According to Counterpoint, a 16Gb LPDDR5 at 7,500 MT/s already in testing, and a later version at 9,600 MT/s with a 4F² cell, with no production date set.
When will CXMT’s first 4F² DRAM arrive?
Its chairman has announced a server DDR5 RDIMM module before the end of 2026, though without public specifications.
Sources:
- Wccftech: Micron calls 4F² a myth, YMTC lines up a 9,600 MT/s prototype
- DIGITIMES: Micron skips 4F² for 3D DRAM as CXMT pushes ahead
- DIGITIMES: China’s YMTC targets 9,600 MT/s with 4F² DRAM design
- Counterpoint Research: YMTC files for landmark IPO, with DRAM next
- Tom’s Hardware: CXMT’s first 4F² DRAM will be a server DDR5 RDIMM
- Sammy Fans: Micron skips 4F² DRAM scaling
