Apple may not have scrapped the M6 Pro and M6 Max after all. New information from the Taiwanese supply chain suggests the company is working on advanced versions of the M6 family that would combine TSMC’s SoIC-MH and WMCM packaging technologies. This directly contradicts earlier reports attributed to Bloomberg’s Mark Gurman, who said Apple had decided to skip those chips in order to speed up the arrival of the M7 Pro and M7 Max. For now, Apple has only officially confirmed the base M6, so both scenarios should be treated as unconfirmed.
The possible M6 Pro and M6 Max in 30 seconds
- Commercial Times reports that Apple is preparing high-end M6 chips using TSMC’s advanced packaging.
- SoIC-MH would increase interconnect density between chiplets, while WMCM would integrate logic, LPDDR memory, and high-speed I/O.
- The report contradicts Mark Gurman, who had said Apple would jump straight from M6 to M7 Pro and M7 Max.
- Apple has officially unveiled only the M6, its first 2 nm chip.
- TSMC is reportedly ramping up packaging capacity to meet future demand.
The discrepancy is especially interesting because it comes just days after Apple officially unveiled its first 2-nanometer processor, the M6, debuting in the new Mac mini, as we covered when Apple unveiled the chip. Apple has confirmed a 12-core CPU, 12-core GPU, two 16-core Neural Engines, and up to 170 GB/s of unified memory bandwidth for this chip.
What Apple hasn’t announced are M6 Pro, M6 Max, or M6 Ultra variants.
That’s where the leaks come in.
Commercial Times reports, citing semiconductor industry sources, that future high-end variants of the M6 family could continue Apple’s shift from large monolithic chips toward more modular architectures, using a combination of SoIC-MH and WMCM.
That’s not a product confirmation, nor does it mean the M6 Pro and M6 Max already have a launch date. The Taiwanese outlet’s own article uses conditional language when discussing future M6 Pro, Max, or Ultra chips.
Apple is discovering that a huge chip isn’t always the best option anymore
The technical shift matters more than the M6 name.
For years, Apple has achieved huge levels of integration by packing the CPU, GPU, Neural Engine, memory controllers, and other blocks into its own System on Chip (SoC) designs.
But the larger a processor gets, the harder and more expensive it can be to manufacture.
A single tiny defect can render an entire die unusable. As die area grows, so does the likelihood of finding defects within each unit produced. Splitting a large processor into several smaller blocks can improve wafer yield and allows different pieces to be combined within the same package.
Apple has already begun moving clearly in this direction.
The company has just unveiled the M5 Ultra as its first four-die design, a fairly clear sign that modularization is no longer just a theoretical possibility within Apple Silicon.
TSMC specifically describes its 3DFabric and SoIC technologies as tools for splitting large SoCs into chiplets and reassembling them through high-density connections. The Taiwanese manufacturer highlights smaller size, higher inter-die bandwidth, and lower power consumption among their advantages over longer conventional connections.
That doesn’t mean all of Apple’s future chips will immediately turn into chiplet designs. The M6 unveiled this week remains a different reference point from the hypothetical professional variants.
What SoIC-MH and WMCM would bring to a future M6 Pro or M6 Max
Commercial Times’ report points to a combination of two different levels of integration.
SoIC, System on Integrated Chips, is TSMC’s technology designed to bond dies with extremely dense connections. TSMC explains that it can integrate chiplets of different sizes, functions, and even manufacturing nodes within a structure that can behave externally like a single SoC.
The goal is to shorten the electrical distances between blocks.
The closer the CPU, GPU, memory, and specialized accelerators sit to one another, the lower the energy needed to move data and the higher the available bandwidth can be. That becomes especially important in AI workloads, where moving large amounts of data between memory and compute units can become a bottleneck.
Commercial Times says Apple could use SoIC-MH to increase interconnect density, while WMCM, Wafer-Level Multi-Chip Module, would be used to integrate components such as logic, LPDDR memory, and high-speed I/O.
The result would be a more modular platform giving Apple more freedom to combine blocks depending on the product.
A hypothetical M6 Pro could use a specific combination of CPU, GPU, and memory, while an M6 Max could add more blocks without necessarily having to manufacture a much larger monolithic die.
It would also allow certain designs to be reused across generations or tiers.
This is precisely one of the general advantages TSMC attributes to its heterogeneous integration technologies: splitting a system into blocks can shorten development cycles because not every component needs to be redesigned at the same time.
The problem: another reliable source says exactly the opposite
This report has to be treated with caution because it contradicts one of the most specific reports published in recent months about Apple Silicon planning.
Mark Gurman said in July that Apple had decided not to release an M6 Pro, M6 Max, or M6 Ultra.
According to that account, the company wanted to speed up the M7 generation because it was preparing major changes aimed at AI processing, including the rumored M7 Ultra chip aimed at turning the Mac into a local AI server. The proposed timeline placed a base M7 during the first half of 2027, followed later by the M7 Pro and M7 Max.
The explanation was unusual but plausible.
Rather than completing the entire M6 family, Apple would have preferred to bring forward an architecture it considered important enough to break its traditional cadence.
Other outlets that reported on Gurman’s information likewise suggested the goal was to speed up the next generation of on-device AI processing.
Commercial Times is now offering a different read.
Its report doesn’t necessarily claim that Apple has recently changed strategy. The supply-chain sources are talking about technologies planned for future high-end chips and opportunities for packaging suppliers.
That difference leaves several possibilities open.
Apple could still be developing M6 Pro and M6 Max designs internally even if it hasn’t decided yet to bring them to market. It’s also possible that technologies initially associated with the M6 end up being used in the M7. Or the packaging sources may know the technical design but not the final commercial name Apple plans to launch it under.
That’s why it’s premature to say the M6 Pro and M6 Max are definitively back.
TSMC is preparing much more advanced packaging capacity
Commercial Times adds another important detail: TSMC is reportedly rapidly expanding its infrastructure dedicated to WMCM and other packaging technologies.
According to estimates cited by the Taiwanese outlet, monthly WMCM capacity could reach roughly 60,000 wafers by the end of 2026 and surpass 120,000 in 2027.
These are supply-chain forecasts, not official figures published by TSMC, so they should be treated as estimates.
The article mentions several Taiwanese facilities involved in that growth. AP6 in Zhunan would play a leading role in SoIC, while AP3 in Longtan would reuse InFO equipment for WMCM, and AP7 in Chiayi would take on WMCM, SoIC, and CoWoS capacity.
That rollout wouldn’t be aimed exclusively at Apple.
TSMC is increasing its advanced packaging capacity to serve an industry where CPUs, GPUs, and AI accelerators are increasingly relying on multi-die architectures.
NVIDIA, AMD, Apple, and ASIC makers all need to bring logic and memory closer together without relying solely on packing more transistors into a single chip.
Packaging is therefore no longer just a relatively simple final manufacturing step — it’s becoming a factor directly responsible for a processor’s performance.
TSMC acknowledges as much in its own documentation: its 3DFabric technologies are aimed at increasing compute density, power efficiency, bandwidth, and integration capacity through systems built from multiple chips.
The M6 already shows Apple wants to accelerate on-device AI
Even though what will happen with the M6 Pro and Max isn’t clear yet, the officially unveiled M6 offers a hint about Apple’s current priorities.
The processor includes Neural Accelerators inside each GPU core, in addition to two 16-core Neural Engines. Apple positions on-device AI processing as one of the main improvements in the new Mac mini.
The company says certain AI workloads can be up to four times faster than on the M4 Mac mini, though the comparison depends on the tests and applications Apple selected.
Memory bandwidth has also increased to up to 170 GB/s in certain configurations.
That figure matters especially for local models. A large language model running on unified memory depends heavily on how fast the GPU and accelerators can access its weights.
Spain’s Mac mini specifications list M6 configurations with 153 GB/s and 170 GB/s, depending on the version.
An M6 Pro or M6 Max architecture would presumably need to raise those figures considerably to justify its place in the MacBook Pro and other professional systems.
Integrating multiple dies and memory through advanced packaging would be a logical way to achieve that without building ever-larger monolithic chips.
But technical logic and a confirmed product are two different things.
Until Apple officially announces its next professional generation, the situation remains open: the Taiwanese supply chain is talking about future high-end M6 chips, while one of the most reliable sources on Apple’s internal plans maintains those products were dropped in favor of the M7.
What seems far less debatable is the underlying trend. Apple Silicon is moving away from the idea that every performance leap has to come simply from building a bigger monolithic chip.
The four-die M5 Ultra, SoIC, and TSMC’s packaging investments all point toward much more modular processors. Whether that transition ends up being called M6 Pro, M7 Pro, or a later generation may end up being a matter of timing rather than technology.
Frequently Asked Questions
Is Apple actually going to release an M6 Pro and M6 Max?
It’s not confirmed. Commercial Times reports on packaging technologies planned for future high-end M6 chips, while Mark Gurman has said Apple decided to skip the M6 Pro and Max to move straight to the M7.
What is SoIC in Apple’s chips?
SoIC is a TSMC 3D integration technology that bonds different dies or chiplets through high-density connections. It can improve bandwidth between blocks and reduce the distances and power consumption associated with communication between them.
What is WMCM?
WMCM stands for Wafer-Level Multi-Chip Module. According to supply-chain reports, Apple could use it to integrate logic, LPDDR memory, and high-speed connections within future processors.
What has Apple confirmed about the M6?
Apple has confirmed the base M6, built on a 2 nm process, with a 12-core CPU, 12-core GPU, two 16-core Neural Engines, and up to 170 GB/s of memory bandwidth. It has not yet announced an M6 Pro, M6 Max, or M6 Ultra.
