AMD and Broadcom have become the leading customers for the future fan-out panel-level packaging (FOPLP) capacity at Powertech Technology (PTI), one of Taiwan’s major semiconductor packaging and testing providers. The company expects to begin mass production in mid-2027 and says a large share of that planned capacity is already committed — another sign that the bottleneck in AI chips is shifting from the silicon itself toward advanced packaging.
Powertech’s FOPLP in 30 seconds
- Powertech expects to begin mass production of FOPLP in mid-2027, with AMD and Broadcom as its lead customers.
- Capacity will grow from around 1,000 panels a month in 2026 to 2,000 in 2027 and roughly 5,000 in 2028.
- Total planned investment could reach NT$70 billion, or roughly €1.9 billion.
- The square panel format lets far more large chips be processed at once than a conventional wafer.
- Powertech is also working on 3D packaging and co-packaged optics components.
Powertech has been working on this technology long before AI drove up demand for large-scale packaging. The company started its experimental FOPLP line in 2016, judged the technology commercially viable in 2018, and later built dedicated facilities to bring it into production.
That bet is now starting to line up with an urgent industry need.
The GPUs and ASICs used in AI are no longer just large chips surrounded by memory. New platforms pack multiple compute dies, chiplets, HBM memory, and complex interconnects into ever-larger packages. Manufacturing them efficiently has become one of the biggest challenges in the supply chain — a strain that’s also showing up in the wider packaging bottleneck squeezing TSMC and its rivals.
FOPLP trades the round wafer for large square panels
The core difference is the manufacturing format.
Most advanced packaging today still relies on 300-millimeter circular wafers. FOPLP moves some of those processes to large rectangular panels, conceptually similar to formats used for decades in other parts of the electronics industry.
Powertech works with panels around 510 x 510 millimeters. The larger usable surface means more devices per manufacturing cycle and less wasted edge space, one of the drawbacks of a circular wafer.
The company argues this architecture improves throughput per batch and can offer an economically attractive alternative for very large packages.
For the Singapore project tied to Powertech, figures of roughly 45 maximum-size AI packages processed on a single panel have been cited, compared with around eight or nine using certain wafer-based processes. Those numbers are specific to that design and shouldn’t be extrapolated to every chip, but they help illustrate the format’s industrial appeal.
Powertech calls its proprietary platform PiFO, and it covers Chip-First, Chip-Last, and Chip-Middle configurations.
The last of those is especially relevant for AI, since it allows SoCs, ASICs, HBM memory, and chiplets to be integrated through high-density redistribution layers (RDL).
Powertech’s own chairman, D.K. Tsai, has conceptually compared some PiFO variants to technologies like TSMC’s CoWoS-L.
They aren’t equivalent products, but they aim to solve a similar problem: connecting huge amounts of silicon within a single system without relying on a full-surface silicon interposer.
AMD will be one of the first major customers
AMD has been linked to the project for months.
Powertech previously confirmed it expects to start supplying chips for AMD’s AI servers using FOPLP during the second half of 2027. The company says installation of the necessary equipment is on track.
The adoption carries an important signal for AMD.
TSMC has built a very strong position in advanced packaging through CoWoS, used extensively by NVIDIA and other AI chip designers. Demand has forced rapid capacity expansion and turned packaging into a strategic piece of accelerator production.
Having alternative technologies doesn’t mean abandoning TSMC or CoWoS. It allows certain products to be diversified and, potentially, helps cut costs or avoid having the entire expansion depend on a single packaging technology.
Earlier reports also suggested AMD was evaluating Powertech’s FOPLP for future architectures, though it’s worth separating those projects — still under evaluation — from the programs whose 2027 production Powertech has publicly acknowledged.
Broadcom’s relationship runs even deeper.
Broadcom and Powertech are building a factory in Singapore
During 2026, Powertech agreed to invest $400 million, around €340 million, to acquire a 30% stake in a joint venture with Broadcom called XCIP Technologies.
The Singapore project involves a total estimated investment of around $5.66 billion, close to €4.8 billion at current exchange rates, and will be dedicated to advanced packaging technologies for AI chips.
Its goals include developing FOPLP and progressively finer-geometry redistribution layers.
Broadcom has become an especially important player in the custom AI ASIC market. Major cloud providers are increasingly designing their own accelerators for specific workloads, creating an opportunity that runs parallel to the conventional GPU market.
FOPLP could be particularly well suited to these kinds of systems, since it allows multiple chiplets, memory, and custom logic to be combined into large-scale packages.
Powertech now says AMD and Broadcom have reserved most of its future capacity, and its chairman says the company doesn’t expect any trouble finding customers through 2030.
From 1,000 to 5,000 panels a month
The production ramp will be gradual.
Powertech expects to have capacity close to 1,000 panels a month during 2026, though it’s still essentially in a phase ahead of large-scale commercial production.
The forecast is to reach roughly:
| Period | Projected FOPLP capacity |
|---|---|
| 2026 | ~1,000 panels/month |
| Mid-2027 | ~2,000 panels/month |
| 2028 | ~5,000 panels/month |
Reaching that last figure will require considerable investment.
Tsai estimates that the construction, engineering, and equipment needed to reach 5,000 panels a month could push cumulative spending to NT$70 billion, roughly $2.2 billion or about €1.9 billion.
The initial line alone would already have required more than NT$20 billion.
Powertech expects to recoup that first investment around mid-2027, as commercial shipments ramp up.
But building large panels doesn’t eliminate the challenges of advanced packaging either.
The big challenge is still manufacturing yield
Moving from a relatively small circular wafer to a panel over half a meter across introduces significant difficulties.
One of them is warpage — panel deformation caused by thermal and mechanical differences between materials. If a surface that large isn’t flat enough, lithography processes and high-density connections lose precision.
Powertech says it has gotten most of that problem under control and now points to process integration and manufacturing yield as the main remaining challenges.
That last point matters a lot.
A modern package can include millions of microscopic interconnects. A seemingly small defect can render useless an extremely expensive device that already contains several advanced chiplets and HBM memory.
Powertech says it has already achieved yields above 90% and aims to push them progressively into the 95% to 99% range. That will be one of the key indicators to watch once the process actually reaches mass production.
FOPLP isn’t trying to replace CoWoS overnight
The growth of panel-level packaging doesn’t mean TSMC’s CoWoS is about to get pushed aside.
CoWoS has years of large-scale production behind it, a huge customer base, and an ecosystem built around some of the most advanced AI chips on the market.
Intel, for its part, uses technologies like EMIB, where small silicon bridges connect different components within the package.
FOPLP is trying to carve out a different niche: achieving high-density interconnects by taking advantage of considerably larger panels to improve throughput and cut costs for certain applications.
Several architectures will likely coexist over the coming years.
| Technology | Key characteristic |
|---|---|
| TSMC CoWoS | Wide adoption in GPUs and AI accelerators |
| Intel EMIB | Localized silicon bridges between chiplets |
| Powertech FOPLP/PiFO | Processing on large square panels |
| 3D packaging | Vertical stacking of different dies |
The choice will depend on package size, chiplet count, HBM memory, connection density, cost, and expected volume.
Powertech is also gearing up for the next battle: optics and 3D
Powertech’s bet doesn’t stop at FOPLP.
The company currently splits its advanced packaging strategy into three main pillars: FOPLP, TSV/3D IC, and optical engines.
Its TSV (Through-Silicon Via) and 3D stacking technology is starting to be used for DRAM and other three-dimensional circuits, with mass production expected from the third quarter of 2026.
In optics, Powertech plans to deliver small quantities of optical engine components for qualification during 2026 and move toward co-packaged optics (CPO) solutions based on silicon photonics during 2027.
That timeline lines up with another shift happening in AI data centers. As the number of connected accelerators grows, moving data over electrical links consumes increasing amounts of energy. NVIDIA, Broadcom, and other manufacturers are already preparing architectures where optical links move ever closer to the networking silicon itself — the same trend visible in NVIDIA’s recent move to bring the memory controller directly into HBM.
FOPLP, 3D packaging, and integrated optics end up being pieces of the same underlying problem.
The race for AI leadership is no longer decided purely by who has the smallest transistor or the GPU with the most FLOPS. Manufacturing, connecting, and powering hundreds of thousands of chiplets is becoming an industry as strategic as designing them in the first place.
The fact that AMD and Broadcom are locking in Powertech capacity even before FOPLP production reaches its planned commercial volume in 2027 shows just how much advanced packaging has become another resource that chipmakers prefer to secure years in advance.
Frequently asked questions
What is FOPLP?
FOPLP stands for Fan-Out Panel-Level Packaging. It uses large rectangular panels instead of limiting certain packaging steps to circular wafers, aiming to process more devices at once and reduce costs.
When will Powertech start making FOPLP chips for AMD?
Powertech expects to begin mass production in mid-2027 and has said the first AMD-related shipments should take place during the second half of that year.
How much capacity will Powertech have?
The company expects to go from around 1,000 panels a month in 2026 to about 2,000 by mid-2027 and reach approximately 5,000 panels a month in 2028.
Will FOPLP replace TSMC’s CoWoS?
Not necessarily. FOPLP offers another way to manufacture large packages and could be competitive for certain designs, but CoWoS remains a widely used and expanding technology. Several architectures and other advanced packaging solutions will likely coexist.
via: Digitimes
