Socionext selects Intel 18A-P for new AI, HPC, and data center chips

Socionext will utilize the Intel 18A-P process to develop new custom SoCs intended for artificial intelligence, high-performance computing (HPC), edge, and data centers. The first announced project will be a high-performance compute chiplet, a significant move for Intel Foundry because it adds an external designer to the evolution of its 18A family and extends its presence beyond Intel’s own processors.

The key highlights of Socionext and Intel 18A-P in 30 seconds

• Socionext will develop custom chips using Intel 18A-P, the highest-performance evolution of Intel 18A.
• The first design will be a HPC chiplet, though client, specifications, and commercial release date have not yet been announced.
• Intel 18A-P maintains RibbonFET and PowerVia and is compatible with 18A design rules.
• Intel has measured up to a 9% performance increase at the same power in a specific test compared to 18A silicon.
• Socionext is pursuing a multivendor strategy and has also announced developments on advanced processes from TSMC.

The announcement is more significant than simply adding another node to Socionext’s roadmap. Intel has been working for years to transform its fabs into a foundry capable of manufacturing chips for external companies. Gaining independent designers’ adoption of its advanced technologies is a key test of whether this strategy can extend beyond Intel’s internal products.

Socionext aligns well with this goal. The Japanese company is fabless, designing semiconductors but relying on external foundries for fabrication. Its business primarily focuses on custom SoCs for clients needing chips optimized for specific applications, from automotive and networking to data center infrastructure.

Now, Intel 18A-P will be an available technology option for such projects.

What’s changed between Intel 18A and 18A-P

Intel 18A is the process platform that underpins much of the company’s effort to regain technological competitiveness in advanced manufacturing.

It combines two major innovations: RibbonFET and PowerVia.

RibbonFET is Intel’s implementation of Gate-All-Around (GAA) transistors, replacing FinFETs and enabling more precise electrostatic control of the transistor channel.

PowerVia moves the main power distribution network to the back side of the chip. This frees space on the front layers for signals and reduces resistance and voltage drops associated with power delivery.

Intel 18A entered production in 2025 and is already used in the company’s products. In January 2026, Intel launched its Core Ultra Series 3 as the first commercial platform manufactured with this technology.

18A-P is an evolution of the same process, not a completely new node.

Initially, Intel announced an expected improvement of around 8% over 18A. Data presented at the June 2026 Symposium on VLSI Technology & Circuits showed that a specific sub-block in ARM architecture achieved approximately a 9% performance increase at the same power, or an 18% power reduction at the same performance, according to Intel.

These results are from internal tests and silicon measurements shared by Intel and do not mean that any chip produced by Socionext will automatically be 9% faster.

The final performance depends on architecture, frequency, size, memory, interconnects, and thermal limits of the product.

Power Boost aims to extract more performance from PowerVia

One of the most interesting new features of 18A-P is Power Boost.

PowerVia already moves the main power distribution to the back side. Power Boost adds a dual-contact architecture where one front contact and one back contact connect to PowerVia.

Intel states that this reduces contact resistance in both NMOS and PMOS transistors, allowing enhanced performance within the same die footprint.

This is especially relevant for AI accelerators.

Large ASICs and data center processors operate with increasing electrical budgets, but performance depends not just on smaller transistors. Delivering stable current within the chip has become a key aspect of design.

Intel also shared new PowerVia data at VLSI 2026, showing 18A maintaining dynamic voltage droop below 10 mV, compared to over 90 mV in Intel 3 with front-side power distribution.

The company claims this reduction can translate to approximately a 5-6% higher frequency or up to 15% less power consumption compared to comparable front-fed technologies.

18A-P also features material changes that Intel says improve thermal resistance by 20-40% in certain scenarios.

For AI and HPC chips where power and cooling are critical constraints, these improvements are particularly significant.

The first project will be an HPC chiplet

Socionext has not yet announced a complete processor.

The first implementation with 18A-P will be a high-performance compute chiplet. The company has not disclosed the client, number of cores, architecture, packaging, or the expected production date.

Choosing a chiplet is not incidental.

AI and HPC processors are increasingly moving away from monolithic dies. Dividing a system into multiple chiplets allows different functions to be manufactured with different processes and connected via advanced packaging techniques.

Intel aims to participate in both segments.

In addition to its manufacturing nodes, Intel Foundry offers technologies like EMIB, EMIB-T, and Foveros for connecting and stacking different dies.

Socionext explicitly mentions leveraging its ASIC expertise alongside Intel’s advanced manufacturing and packaging roadmap.

This leaves open the possibility that future projects may use not only 18A-P to produce specific chiplets but also Intel’s packaging infrastructure to incorporate memory or other components. However, the companies have not yet specified which packaging solution the initial design will employ.

Socionext is not exclusive to a single foundry

Another important detail is that this agreement does not make Intel Socionext’s sole manufacturer.

The Japanese company plans to work with multiple foundries depending on the project.

In fact, on July 1, 2026, Socionext announced plans to develop advanced data center SoCs using TSMC A14, the upcoming angstrom generation from TSMC.

This provides a comparison within Socionext’s own roadmap: one path involves access to Intel 18A-P, while another prepares designs for TSMC’s most advanced nodes.

Maintaining multiple options can be especially valuable for custom ASIC clients, allowing them to choose the process based on performance, power, cost, schedule, capacity, packaging, or manufacturing region requirements.

For Intel, the key is that 18A-P now enters the list of processes that independent designers consider sufficiently competitive for AI and data center offerings.

This does not mean large-volume production is happening yet.

Socionext has not disclosed how many projects will use 18A-P or the size of future contracts.

Intel Foundry needs external customers to validate its model

The strategic importance of this announcement directly impacts Intel Foundry’s future.

The company has advanced fabs and has spent years developing nodes to compete with TSMC and Samsung. But becoming a true foundry requires more than just manufacturing good chips for internal use.

It must attract external companies to design around its rules, IP, EDA tools, and processes.

Intel has been building this ecosystem through agreements with Synopsys, Cadence, Siemens EDA, and specialized design and chiplet companies. Compatibility between 18A and 18A-P is part of this effort, enabling reuse of much of the initial design work.

Socionext adds another piece: a company whose business is creating custom silicon for third parties.

Rajinder Cheema, Socionext’s CTO, states that the company will use 18A-P to meet the performance and power needs of AI, HPC, and data centers. John Zucker, Business Development Lead for Intel Foundry, also mentions collaboration in AI acceleration and Physical AI.

These are business objectives for both companies and will likely translate into products in the future.

Unlike more generic announcements, here a first development has already been identified: a HPC chiplet.

18A-P is becoming a key test for Intel’s foundry

Intel 18A has already demonstrated its capability to produce products for Intel, with manufacturing ongoing in the US.

18A-P’s role is different.

It must show that the platform can evolve to offer more performance without forcing designers to rebuild their products from scratch, and that Intel can turn this technology into an attractive offering for external clients.

The inclusion of Socionext does not yet suggest that Intel has gained significant market share over TSMC.

But it does send a more concrete signal than just a statement of intent.

A company specializing in custom chips is preparing HPC silicon on 18A-P while continuing to work with TSMC’s advanced processes.

For Intel Foundry, winning more such projects will likely be as important as any performance figures from the process itself.

Frequently Asked Questions

What has Socionext announced with Intel?

Socionext will use Intel’s 18A-P process to develop custom SoCs for AI, HPC, edge, and data centers. The first project will be a high-performance compute chiplet.

What’s the difference between Intel 18A and 18A-P?

18A-P is an evolution of Intel 18A that maintains RibbonFET and PowerVia and is compatible with its design rules. It adds device, contact, interconnect improvements, and Power Boost features to enhance performance.

How much does Intel 18A-P improve performance?

Intel showed in June a roughly 9% performance gain at the same power in a specific ARM-based sub-block compared to 18A, or an 18% power reduction at the same performance. These results are from specific tests and do not automatically apply to all products.

Will Socionext stop using TSMC?

No. Socionext works with multiple foundries and has also announced plans to develop data center SoCs using TSMC A14, the upcoming TSMC process node. The addition of 18A-P broadens its manufacturing options.

via: socionext