NVIDIA is evaluating reducing the amount of HBM memory planned for Rubin Ultra, its future generation of artificial intelligence accelerators, amid the DRAM shortage, rising memory costs, and the difficulty of manufacturing the most complex configurations. TrendForce confirms that the company is studying 8-layer and 12-layer alternatives in both HBM4 and HBM4E, though the final specification hasn’t been decided yet. The possibility of using less memory per GPU also raises a deeper question: AI workloads are starting to depend more on bandwidth and a full memory hierarchy than on storing absolutely all the data in HBM.
NVIDIA Rubin Ultra’s memory shift: the key points in 20 seconds
- NVIDIA is studying alternatives to the 12-Hi HBM4E originally planned for Rubin Ultra.
- The options on the table include 8-layer and 12-layer HBM4E and HBM4 configurations.
- TrendForce points to DRAM scarcity, costs, and manufacturing yields as the main reasons.
- Fewer layers make it possible to produce more HBM stacks from a similar amount of wafers.
- The final specification is still not locked in.
The shift is especially striking because Rubin Ultra had been introduced around a seemingly opposite idea: packing huge amounts of memory next to the processor. During 2026, talk went as far as configurations of up to 1TB of HBM4E, but the state of the memory market is now forcing a rethink of just how far it makes economic sense to keep pushing capacity.
That doesn’t mean HBM is losing importance. The available data actually points the other way: demand keeps outpacing production capacity, and TrendForce estimates that shipped HBM bits will grow between 50% and 60% year over year in 2027, still below the expected rise in demand.
From 12 to 8 layers to build more accelerators
HBM stands for High Bandwidth Memory. Its main characteristic is that it uses several DRAM chips stacked vertically and connected through through-silicon vias (TSVs), which delivers huge bandwidth while taking up relatively little space next to the processor.
But manufacturing those stacks is far more complex than producing conventional DRAM.
The more layers you add, the more demanding manufacturing, assembly, and validation become. A problem with any single component can drag down the yield of the whole stack.
TrendForce specifically points to two difficulties for Rubin Ultra. On one hand, it expects global DRAM supply to stay tight through 2027, limiting the wafers Samsung, SK hynix, and Micron can dedicate to HBM. On the other, there are still uncertainties about validation timelines and yield improvements for 12-layer HBM4E.
NVIDIA used a 12-Hi HBM4E configuration as the reference design for Rubin Ultra throughout 2025 and the first half of 2026. Since the start of the third quarter, it has widened the options under study to 8-Hi HBM4E, 12-Hi HBM4, and 8-Hi HBM4.
The company hasn’t announced which one it will ultimately use.
Cutting the number of layers has a fairly straightforward advantage: a given amount of DRAM dies can be turned into more memory stacks.
An eight-layer configuration needs fewer dies than a twelve-layer one. If DRAM supply is constrained, that makes it possible to produce memory for a larger number of accelerators.
For NVIDIA, the decision therefore comes down to a trade-off between memory capacity per GPU and the number of GPUs that can actually reach the market.
TrendForce believes boosting I/O speed will be one of Rubin Ultra’s priorities. If HBM4E clears validation in time, per-pin speed could rise from Rubin’s current 8-11.7Gb/s to roughly 14-16Gb/s. An optimized HBM4-based solution would land at around 11-12Gb/s, according to the firm’s estimates.
Memory can be smaller and, at the same time, faster.
AI no longer needs to keep everything in HBM
There’s also a technical shift that helps explain why cutting capacity doesn’t necessarily carry the impact it would have a few years ago.
AI models are moving away from treating HBM as the only place where all the information needed to operate has to live.
NVIDIA itself has developed architectures where different types of memory and storage take on different roles.
HBM remains the fastest tier, closest to the GPU, reserved for the data the processor needs immediately. But other pieces of data can move to LPDDR, CXL-attached memory, or NAND storage, depending on the workload and how often that data actually needs to be accessed.
NVIDIA already applies this principle to context memory.
The Vera Rubin platform includes an architecture called the Inference Context Memory Storage Platform, designed to use flash storage connected via BlueField-4 as an extension of the memory hierarchy during inference workloads with large amounts of context.
Software evolution is also reducing certain requirements.
Techniques like quantization make it possible to represent model weights using fewer bits. Other architectures reduce the amount of memory needed to maintain the so-called KV cache, one of the components that can consume the most capacity during inference on large models.
The split between prefill and decode — two distinct phases of inference that can run on different resources — is also growing.
The result is a much more complex hierarchy.
The GPU keeps in HBM the data set it needs to work on immediately, while less frequently used information can sit in cheaper, higher-capacity tiers.
This doesn’t mean having more HBM has stopped being useful.
The current Rubin offers 288GB of HBM4 per GPU and up to 22TB/s of bandwidth, figures that show just how central memory remains to the architecture. NVIDIA specifically highlights higher bandwidth as one of the elements that make it possible to work with models that have several trillion parameters and large context windows.
The difference is that, once the minimum capacity needed to keep the active data set has been reached, increasing bandwidth can deliver more performance than continuing to add capacity.
Less HBM per GPU doesn’t mean less business for manufacturers
Rubin Ultra’s possible memory reduction might initially look like bad news for Samsung, SK hynix, and Micron.
The reality is less clear-cut.
If cutting from twelve to eight layers improves manufacturing yield and allows memory to be produced for a larger number of accelerators, NVIDIA could end up selling more GPUs.
More accelerators also mean more HBM stacks installed in absolute terms.
There’s also no clear sign for now that the market is heading toward an immediate supply glut. TrendForce expects DRAM to stay constrained through 2027 and believes HBM suppliers will retain pricing power during that period.
Micron, for example, began volume production of 12-layer, 36GB HBM4 for NVIDIA Vera Rubin during the first quarter of 2026, with per-pin speeds above 11Gb/s and more than 2.8TB/s of bandwidth per stack. It has also shipped samples of 16-layer, 48GB HBM4.
The industry can build increasingly large stacks. Whether it makes sense to use them in every product is a separate question.
That distinction matters for understanding the decision NVIDIA is weighing.
Cutting HBM in Rubin Ultra doesn’t necessarily mean the industry has found a better alternative, nor that the so-called memory wall — the problem of feeding increasingly fast processors with data quickly enough — has gone away.
What it shows, rather, is just how costly it has become to try to solve that problem simply by piling ever-larger amounts of the fastest available memory next to each GPU.
The analysis shared by the original source goes further, suggesting HBM may have softened the traditionally cyclical nature of the DRAM market by absorbing large amounts of manufacturing capacity. It also argues that a future architecture could end up integrating increasing amounts of memory and logic together. These are interpretations about where the industry is headed, not specifications confirmed by NVIDIA.
For now, there’s something more concrete: NVIDIA is studying using less HBM in Rubin Ultra while trying to keep I/O speeds higher.
And it’s not the only one.
TrendForce notes that several cloud service providers are also evaluating reducing the HBM capacity of their own upcoming AI ASICs.
The accelerator race may be entering a different phase as a result. In recent years, every generation added more capacity and more bandwidth. Memory scarcity and pricing are now forcing a decision about which part of that capacity actually delivers enough performance to justify its cost.
The question is no longer simply how much HBM can be placed next to a GPU. What also matters now is how much of it actually needs to stay there, and how fast the processor can receive that data.
Frequently asked questions
Has NVIDIA definitively decided to reduce Rubin Ultra’s memory?
No. TrendForce confirms that NVIDIA is evaluating several configurations, including 8-layer HBM4E and 8- or 12-layer HBM4, alongside the original 12-layer HBM4E design. The final configuration hasn’t been announced yet.
Why does NVIDIA want to use less HBM?
The analyst firm mainly points to the expected DRAM shortage through 2027 and uncertainties around validation and manufacturing yields for 12-layer HBM4E. Reducing stack height would also make it possible to produce memory for more GPUs.
Does HBM speed matter more than capacity?
It depends on the workload. Capacity is still needed to keep active data in place, but newer AI architectures let less-used data move to other memory and storage tiers. That raises the importance of the bandwidth of the HBM that stays right next to the GPU.
Will cutting HBM hurt Samsung, SK hynix, and Micron?
Not necessarily. If shorter stacks improve manufacturing yield and allow more accelerators to be sold, total HBM demand could keep rising. TrendForce expects HBM bit shipments to grow between 50% and 60% in 2027, with supply still falling short of demand.
via: Jukan05
