The technology gap between Chinese and South Korean memory makers has narrowed quickly. The Korea Semiconductor Industry Association (KSIA) estimates China is now roughly a year behind in NAND, two years behind in DRAM, and three years behind in HBM (High Bandwidth Memory). YMTC and CXMT are driving this progress, though measuring competitiveness in years simplifies important differences in manufacturing yield, capacity, efficiency, and large-scale production.
China’s memory progress in 30 seconds
- The KSIA estimates the China-South Korea gap has narrowed to a year in NAND, two years in DRAM, and three years in HBM.
- YMTC is competing increasingly close to Samsung and SK hynix in NAND and is working on generations with more than 400 layers.
- CXMT is already producing DDR5 and LPDDR5X while advancing in HBM.
- In HBM, manufacturing and packaging difficulties persist that keep CXMT behind the leaders.
- China’s capacity growth can increase competitive pressure even where the technology isn’t equivalent.
The estimate is especially notable because just a few years ago China’s lag in some memory segments was put at around five years. This doesn’t mean YMTC or CXMT have caught up with Samsung Electronics and SK hynix on every metric, but it shows the gap can no longer be measured solely by the ability to make older products more cheaply.
A 2025 report from the Korea Institute for International Economic Policy (KIEP) had already flagged this trend. The institute noted at the time that CXMT had started producing 16nm-class DDR5 DRAM and that YMTC was making NAND with around 300 layers, putting it much closer to South Korean manufacturers.
YMTC Turns NAND Into China’s Most Advanced Front
NAND memory is currently the area where the gap looks smallest.
According to estimates reported by South Korean media, Samsung and SK hynix moved toward roughly 300-layer generations during 2025, while YMTC sat around 270 layers.
Based on this progress, the KSIA calculates a gap of roughly one year.
YMTC is also working on NAND with more than 400 layers for its next generation. Successfully developing it doesn’t automatically mean it can manufacture it right away at the same volume, yield, or cost as its competitors, but it shows how far its technology has advanced.
One of its key tools is Xtacking, the architecture YMTC developed to manufacture the NAND memory array and the peripheral logic separately before joining them.
This approach allows both parts to be worked on independently and then connected later using advanced bonding techniques.
The shift toward hybrid bonding becomes especially important as the number of layers and density increase.
There are also commercial signs that YMTC is no longer a marginal player. Several 2026 market studies rank the Chinese manufacturer among the world’s leading NAND suppliers by bit volume shipped, and the company’s parent has even begun preparing a major Shanghai IPO to fund that growth.
So talking about a roughly one-year gap doesn’t mean the technologies are identical, but it reflects a major shift from the position the Chinese industry held just a few years ago.
CXMT Already Competes in DDR5, But HBM Is a Different Story
ChangXin Memory Technologies’ (CXMT) progress is arguably more significant for the DRAM market.
The Chinese company started with products well behind the most advanced generations from Samsung, SK hynix, and Micron. That’s changing.
CXMT has moved into DDR5 and LPDDR5X and continues developing smaller DRAM process nodes.
The KSIA now puts the gap in conventional DRAM at around two years.
| Technology | Estimated China-South Korea Gap |
|---|---|
| NAND Flash | ~1 year |
| DRAM | ~2 years |
| HBM | ~3 years |
These figures should be understood as industry estimates, not a mathematical equivalence between generations.
Two manufacturers can both sell DDR5 and still get different results in density per wafer, power consumption, frequency, manufacturing yield, or costs.
The same goes for the process node used. Commercial naming and nanometer figures alone don’t describe every characteristic of a DRAM technology.
The gap becomes even more evident when it comes to HBM.
A 25% Yield Shows the Problem China Still Has With HBM
High Bandwidth Memory is one of the most in-demand components for AI infrastructure.
HBM stacks several DRAM dies in a three-dimensional structure and connects them using advanced packaging techniques. The result delivers far greater bandwidth than conventional memory and feeds data to GPUs and AI accelerators.
But manufacturing HBM is considerably more complex than producing a DDR5 module.
CXMT is working in this area, and various reports point to HBM3 and HBM3E development. However, the known yield figures show the gap with the leaders remains significant.
SemiAnalysis estimates cited by various outlets have put the overall yield of certain CXMT HBM stacks at around 25% during their development phase.
The figure hasn’t been officially confirmed by the company, and it shouldn’t be automatically extrapolated to all of its HBM products.
It does illustrate the industrial problem, though.
With HBM, it’s not enough to manufacture each DRAM die correctly. The layers must be stacked, connected, and then pass packaging and validation stages. A defect in any one component can ruin a structure that’s far more expensive than a conventional DRAM chip.
CXMT also has to master technologies like TSVs (Through-Silicon Vias), vertical connections that run through the silicon and let the stacked dies communicate with each other.
That’s why the KSIA still puts the HBM gap at around three years, wider than in NAND or conventional DRAM.
South Korea holds an especially strong advantage here thanks to SK hynix and Samsung, while Micron is the third major international manufacturer.
EUV Restrictions Haven’t Stopped China’s Progress
YMTC and CXMT’s progress also raises questions about the limits of the technology controls applied to China.
Western restrictions make it harder for Chinese manufacturers to access certain advanced manufacturing equipment, especially ASML’s extreme ultraviolet (EUV) lithography systems.
China still relies heavily on foreign equipment at several stages of production, and both companies have reportedly been stockpiling ASML deep ultraviolet machines to lock in years of expansion capacity.
However, memory and logic processors present different challenges.
Chinese manufacturers can stretch deep ultraviolet (DUV) lithography further, tweak processes, resort to multiple-patterning exposures, and develop new integration and packaging techniques to advance without the same tools their competitors have.
That adds complexity and can hurt costs or yield, but it doesn’t necessarily stop the product from improving.
Hybrid bonding is especially interesting because it allows density and connectivity gains to come from packaging and architecture, not just from shrinking transistor size.
That’s why measuring China’s capability just by whether it has EUV or not falls short.
Production Capacity Can Matter as Much as Technology
There’s another dimension to China’s progress that doesn’t depend directly on having the most advanced memory: making it in large quantities.
CXMT is rapidly expanding its DRAM capacity. Reuters reported in July 2026 that the company had already become the world’s fourth-largest DRAM maker and was growing its presence by taking advantage of the shortage caused by strong memory demand.
YMTC is doing something similar in NAND.
Concrete estimates of future capacity vary widely by source. Some reports point to expansions toward several hundred thousand wafers a month at both CXMT and YMTC, but these are forecasts that depend on new fabs, equipment availability, and how fast production ramps up.
That’s why it isn’t wise to treat figures like 600,000 or 800,000 wafers a month for CXMT, or 500,000 for YMTC, as confirmed until those facilities are actually operating.
The overall direction, however, is clear: both manufacturers are expanding capacity.
This can have consequences even before they catch up technologically with their competitors.
Memory doesn’t need to be the most advanced on the market to compete in personal computers, conventional servers, phones, SSDs, or other electronic devices.
The memory market depends heavily on volume and price.
Catching Up With Samsung and SK hynix Takes More Than Matching Generations
The one-, two-, or three-year figures make it easy to visualize China’s progress at a glance, but they also risk oversimplifying it.
A memory manufacturer has to master process, architecture, yield per wafer, reliability, packaging, power consumption, speed, and large-scale production all at once.
HBM adds three-dimensional integration, thermal management, and extremely complex connections on top of that.
That’s why producing a sample of HBM3E isn’t the same as competing commercially with millions of HBM3E units made at good yields.
The same applies to 400-layer NAND: layer count is an important metric, but it doesn’t by itself determine performance, density, latency, endurance, or cost per bit.
China’s situation matters precisely because YMTC and CXMT are starting to advance on several of these dimensions at once.
They also have a huge domestic market to draw on. Chinese makers of servers, phones, computers, and AI systems can provide a customer base that lets them grow volume, learn from production, and fund new generations.
Trade restrictions can indirectly reinforce that dynamic by encouraging the substitution of foreign components within China.
That’s why the picture painted by the South Korean industry is more meaningful than simply claiming China has caught up with the West.
Significant technology gaps still exist, especially in HBM and certain manufacturing equipment, but the gap in conventional memory has narrowed much faster than seemed likely just a few years ago.
In NAND, YMTC is already competing close to the leaders on some metrics. In DRAM, CXMT has moved from older generations to DDR5 and LPDDR5X. HBM remains the hardest step.
If the KSIA’s estimate is right, South Korea’s lead can no longer be measured in a decade, or even five years: it currently stands at around three years in HBM, two in DRAM, and just one in NAND.
