AMD will add Universal Chiplet Interconnect Express (UCIe) 1.1 to select Versal RF devices, a move that will allow specialized chiplets of different types to be connected directly within the same package. The company expects the first compatible production chiplets to be available alongside select Versal RF Series devices in the fourth quarter of 2027.
UCIe on AMD Versal RF in 30 seconds
- AMD will bring UCIe 1.1 natively to select Versal RF adaptive SoCs.
- The platform will support up to four UCIe-SP interfaces and two UCIe-AP interfaces.
- Aggregate in-package bandwidth could reach several terabits per second.
- Connected chiplets could be dedicated to AI, RF, CPU, GPU, security, communications, or custom ASICs.
- The first compatible production devices are expected in the fourth quarter of 2027.
The announcement fits an increasingly visible trend in semiconductors: moving away from building complete systems as a single large block of silicon and instead combining specialized chiplets within the same package.
AMD has used this approach in CPUs and GPUs for years, but the novelty here is different. Versal RF will be able to act as a kind of adaptable core to which other chiplets connect through an open standard, avoiding the need for each integration to rely on a different proprietary interface.
UCIe was created for exactly that: letting different blocks of silicon communicate within the package through a common, high-speed interface.
Up to six UCIe links on select Versal RF devices
The first UCIe 1.1-compatible Versal RF devices will support two types of connections.
On one hand, there will be up to four UCIe-SP interfaces, aimed at standard packages. Each will use 16 lanes and will be able to run at up to 16 GT/s.
On the other hand, AMD plans up to two UCIe-AP interfaces, designed for advanced packages with an interposer. In this case, each interface will use 64 lanes and will be able to reach up to 8 GT/s.
Combined, the company says aggregate bandwidth within the package itself could reach several terabits per second.
The physical difference is also significant.
For UCIe-SP, AMD is proposing a chiplet with a 130-micron bump pitch on a standard organic substrate. For UCIe-AP, integration moves to 45-micron microbumps on a silicon interposer.
That allows for higher connection densities and lets chiplets sit much closer to one another.
Versal RF aims to become a chiplet platform
Versal RF already combines several functions that would normally require separate devices, building on the memory-on-package integration AMD introduced for Versal earlier this year.
It includes RF converters, dedicated digital signal processing blocks, AI engines, and programmable logic. AMD puts its capacity at up to 80 TOPS of heterogeneous DSP processing.
The company also says certain configurations can bring together, in a single package, functions that previously required up to six separate devices.
Adding UCIe expands on that approach.
Instead of packing all functionality into a single design, a manufacturer will be able to connect additional chiplets to Versal RF to cover very specific tasks.
AMD cites, among others:
- RF front-ends and data converters;
- artificial intelligence accelerators;
- CPUs;
- GPUs and specialized compute;
- security engines;
- communications processors;
- application-specific ASICs.
The idea is that these blocks could come from either AMD or third parties, as long as they properly implement UCIe.
Less board, more in-package integration
Until now, many of these functions were connected at the board level.
That requires serdes interfaces, longer traces, connectors, and additional logic, at a cost in latency, power consumption, and physical footprint.
Moving those connections inside the same package changes the architecture.
AMD says UCIe will cut latency and improve power efficiency compared with its serialized GTM2 interfaces used at the board level. These are the manufacturer’s own internal comparisons, so they should be treated as AMD’s own estimates rather than a universal advantage over any other architecture.
The industry logic, however, is clear: the shorter the distance between blocks exchanging huge amounts of data, the lower the energy cost of moving each bit can be.
This matters especially in AI, RF, and telecommunications, where moving data is starting to consume a growing share of a system’s total energy.
UCIe can avoid having to redesign an entire SoC
One of the biggest attractions of the chiplet approach is economic.
Developing an advanced monolithic SoC is expensive and time-consuming. Each new variant aimed at a customer or application can force a significant part of the design to be redone.
With chiplets, a manufacturer can reuse blocks that have already been validated.
For example, a Versal RF device could keep its programmable logic and signal processing and later be combined with an AI accelerator built for a specific customer, a security ASIC, or a communications processor.
That doesn’t eliminate integration work or turn chiplets into fully interchangeable parts. Signal, power, memory, packaging, thermal, and software validation are still required.
But it does make it possible to separate certain functions and reuse them across more products.
UCIe’s goal is precisely to enable that reuse through a common interface between the different blocks.
AI is only part of the goal
Although AMD includes AI accelerators among the possible connected chiplets, Versal RF is also clearly aimed at other markets.
The company mentions Electromagnetic Spectrum Operations (EMSO) applications, AI-accelerated analog RF processing, instrumentation, testing, and communications.
That includes systems where latency between signal acquisition and processing is especially sensitive.
Another technology that could gain importance in the coming years also shows up: co-packaged optics (CPO), a technique already being deployed to cut the electrical distance between fiber and chip in AI networks.
The applications diagram AMD released includes optical interfaces and fiber as one of the possible elements that could be connected through chiplets.
The approach makes sense as networks and accelerators need to move more data. Bringing optical components closer to processing chips can reduce electrical distances and power consumption.
UCIe is trying to become the USB of chiplets, but it isn’t there yet
UCIe has the backing of a large part of the semiconductor industry and aims to solve one of the hardest problems in the chiplet model: interoperability.
The theoretical goal is appealing. A designer could pick different specialized blocks and combine them within a package in a way similar to how components are integrated today through external standards.
In practice, chiplet integration remains far more complex.
Even if two pieces of silicon both use UCIe, that doesn’t mean they can be connected automatically. Physical, thermal, electrical, power, coherence, software, and packaging issues all still need to be resolved.
That’s why AMD’s announcement should be understood as a step toward more modular systems, not as the immediate arrival of a market where any chiplet can be combined with any other.
Even so, adding UCIe to Versal RF matters because AMD is carrying the chiplet architecture from CPUs and GPUs over to specialized adaptive systems.
And that opens up an interesting possibility: instead of designing a new SoC for every RF, communications, or AI application, companies could build custom packages from already existing blocks.
If UCIe manages to mature as a standard and the supply of compatible commercial chiplets grows, that model could shorten development times for new systems.
AMD will start with select Versal RF devices and has said it will add UCIe to other adaptive SoCs as the market progresses. The real test will come starting in 2027, when these designs move from announced architectures to packages produced at scale.
Frequently Asked Questions
What is UCIe?
UCIe, Universal Chiplet Interconnect Express, is an open standard for connecting chiplets within the same package through high-speed, low-power links.
How many UCIe interfaces will AMD Versal RF support?
Select models will support up to four UCIe-SP interfaces and up to two UCIe-AP interfaces, with aggregate bandwidth of several terabits per second.
What kinds of chiplets will be able to connect?
AMD lists AI accelerators, CPUs, GPUs, RF converters, communications processors, security engines, and custom ASICs, along with other UCIe-compatible components.
When will the first Versal RF devices with UCIe be available?
AMD expects the first compatible production chiplets to be available with select Versal RF Series devices during the fourth quarter of 2027.
