The White House’s ambition to balance semiconductor manufacturing for the U.S. market on a 50/50 basis between the United States and Taiwan faces a fundamental obstacle: the U.S. still lacks a mature domestic supply chain — from critical materials to advanced packaging — capable of supporting such an aggressive share of leading-edge nodes (EUV) that now power AI, 5G, mobile devices, and data centers.
The proposal, publicly championed by Commerce Secretary Howard Lutnick, aims for half of the chips used by American companies and consumers to be manufactured in plants located within the country. The strategic logic is clear: reduce dependence on the island in a crisis scenario and boost deterrence and defense capabilities of Taiwan without hostage-ing silicon supply. Meanwhile, the administration links this goal to security commitments and applies 100% tariffs on imported semiconductors, with exemptions for investments in U.S. factories (such as TSMC or Samsung).
An Unspecified Operational Goal
However, the plan lacks a workable definition, according to officials and analysts in Taipei. “50/50” of what? Only advanced nodes, or also mature nodes? Does it include advanced packaging (2.5D/3D), memory, or just logic? Does it encompass all consumption in the U.S., or a subset for governmental/strategic use? Without such a framework, there’s no metric to discuss feasibility, costs, timelines, or incentives.
Analyst Ming-Chi Kuo summarizes it thus: without specifying product families, technology levels, and destinations, the “50/50” becomes a slogan but lacks planning. That is why Cheng Li-Chun, Taiwan’s vice prime minister, denies formal negotiations have taken place on those terms.
The Actual State of U.S. Industry
It’s important to separate volume from cutting-edge. The U.S. already manufactures a large volume of chips in mature nodes (automotive, power, industrial) through Analog Devices, Texas Instruments, GlobalFoundries, onsemi, and SkyWater; in terms of units and revenue, they represent the majority of the market. Additionally, Intel produces advanced logic chips domestically, and TSMC and Samsung are expanding their fabs in Arizona and Texas.
The bottleneck, however, resides in frontier EUV nodes (N5/N4/N3 now; N2/A16 future) and in advanced packaging (CoWoS, HBM with interposer, hybrid bonding). Here, Taiwan — primarily TSMC — concentrates around ≈ 90% of global production and sets the standards. Moving 50% of everything consumed by U.S. companies into domestic factories mixes categories and diverts focus from the real challenge: autonomy in leading-edge manufacturing and a local ecosystem to support it.
TSMC in Arizona: Real Acceleration, Tangible Limits
TSMC’s expansion in Arizona — the largest foreign investment in U.S. semiconductors history — is progressing faster than expected. The public plan includes six fabs on advanced nodes, two packaging plants, and a R&D center. Fab 21 (phase 1) began production in 2024; phase 2 has been brought forward to 2H 2027 with node upgrade (N3→N2 and even A16, at Washington’s request). Kuo projects that the first three fabs will reach high utilization by 2028–2030.
Nevertheless, with everything in motion, TSMC-USA would account for ≈ 10–15% of its global capacity by 2030, and about 25–30% when all six phases are operational around 2032. Adding Intel (Arizona, Ohio) and Samsung (Texas), the U.S. could cover a significant portion of its leading-edge demand; but the “50/50” remains distant without a local ecosystem of materials, equipment, and packaging at comparable scale.
The Missing Piece: Upstream Providers and Materials
Autonomy is not just about building fabs. The supply of ultra-high-purity photoresists, underfills, coatings, slurries, and wet chemicals still heavily depends on Japan (JSR, Namics, Nagase, etc.). Today, they ship to Arizona to support Fab 21, but as capacity grows, plants or logistics hubs in the U.S. would be needed to avoid tariffs and increase flexibility. Setting up such infrastructure takes years, and outside Asia, the market remains too small to justify immediate investments.
The same issue applies to critical equipment: lithography (Netherlands), metrology, and deposits (Europe and Japan) are irreplaceable. Without parallel localization of materials and supply chain, moving wafers to the U.S. merely shifts geographic vulnerabilities.
Is it Economically Feasible?
From a cost perspective, producing half of the chips consumed in the U.S. on U.S. soil is more expensive: even with proven nodes (N5/N4), manufacturing in Arizona can entail an ≈ 30% premium over Taiwan. Companies like Apple, AMD, or NVIDIA might absorb this, but not all can. Additionally, Asia benefits from dense ecosystems (materials, tool vendors, maintenance) that lower logistics costs and shorten downtime. In the U.S., rebuilding this network and developing local expertise takes time.
The logic shifts if viewed as a risk mitigation policy. The U.S. consumes about 25–33% of global semiconductors, produces around 10–12%, and its cutting-edge capacity remains limited. A disruption in Taiwan — conflict, blockade, earthquake — would impact cloud (hyperscalers), defense, healthcare, and automotive. In this lens, paying more for silicon enhances resilience; the industrial ROI is realized in the long run through cascading effects — suppliers, talent, R&D.
Politics and Symbols: “Reshoring” as Narrative
For the administration, chip sovereignty is a symbol of industrial revival. Announcements from Intel, TSMC, and Samsung, the figure of $165 billion attributed to TSMC, and the acceleration of nodes in Arizona fuel this narrative, though many decisions originated in prior political cycles, and its full realization is years away. Meanwhile, the “50/50” acts as a negotiating message with Taipei, combined with tariff leverage.
Can “50/50” Really Be Achieved?
Aspirational, yes; short-term viability, unlikely. TSMC now manufactures more leading-edge chips than the rest of the world combined. Matching this pace would require multiple “mega-sites”, tens of thousands of advanced tools, and hundreds of thousands of skilled workers — volumes that the U.S. currently does not have. The labor pipeline for advanced manufacturing remains short, sector leaders warn: building fabs will be slow, and operating them costly, unless training is scaled up.
The practical path involves defining what “50/50” covers (by families and nodes), prioritizing leading-edge and packaging, ramping up TSMC/Intel/Samsung in the U.S., and pushing Japanese and European suppliers to localize some of their production. The achievable goal by early 2030s: that Arizona, Ohio, and Texas supply a substantial part of domestic demand for leading-edge nodes, while fostering the materials and equipment supply chain.
What to Watch in the Next 24–36 Months
- TSMC-USA ramp-up: yields, N2/A16 nodes, and CoWoS/SoIC capacity on U.S. soil.
- Intel Foundry: execution of Intel 3/18A and external contracts confirming confidence in its roadmap.
- Samsung Texas: schedule and nodes for its second wave (and advanced packaging capabilities).
- Materials: decisions by JSR, Namics, Nagase, and others regarding plants or hubs in the U.S.
- Workforce: technical training programs (community colleges, apprenticeships) and visa policies to attract talent.
- Tariffs and incentives: how 100% tariffs are applied and what exemptions are available for investments.
- Memory: plans from Micron (DRAM) and SK hynix (HBM assembly in the U.S., possibly locally?) to prevent cutting-edge logic from falling behind in memory technology.
Core Issue: From “Where” to “How”
The real debate isn’t about where a chip is manufactured, but how to orchestrate a complete value chain: raw materials, equipment, fabs, memory, packaging, logistics, talent, and anchor customers. Without this comprehensive vision, the “50/50” is just slogan. With it, it could be a partial milestone within a broader strategy: multiple vertically integrated poles (U.S., Taiwan, allies) that reduce systemic risk without undermining the efficiency of a global, interdependent ecosystem that, whether we like it or not, will continue to be interconnected.
Key Takeaways
- Political goal: increase domestic chip production by >40% before the current administration’s term ends.
- Tools: negotiations with Taipei, 100% tariffs (with investment exemptions), CHIPS Act subsidies, and pressure to accelerate nodes in the U.S.
- Reality: The U.S. produces many chips (mature nodes), but lacks EUV logic and advanced packaging; the main bottleneck is ecosystem, not just the fab.
- Outlook: With TSMC/Intel/Samsung established and local suppliers in place, early 2030s could see a significant portion of the national demand for leading-edge nodes met.
Frequently Asked Questions
Why isn’t just bringing fabs to the U.S. enough?
Because without localized materials (photoresists, underfills), equipment, and packaging, the chain remains dependent on Asia and Europe. Fabs alone don’t guarantee resilience.
What exactly does “50/50” mean?
It’s not defined yet. To be operational, it must be specified by families (logic vs. mature nodes), memory, packaging, and destinations (total U.S. consumption, government use, critical sectors). Without this, it’s impossible to measure.
Who would lose with a 100% tariff?
Probably small manufacturers with limited investment capacity in the U.S. and clients who buy chips from mature nodes where local production suffices. Big players (TSMC/Samsung) would likely get exemptions due to their investments.
When could the U.S. cover “a large part” of its leading-edge demand?
If TSMC Arizona, Intel, and Samsung follow their schedules, the significant leap would be around 2028–early 2030s. By then, the focus should broaden to local materials and packaging.
via: tomshardware