The AI war is no longer fought solely at the manufacturing node or GPU performance. Increasingly, a crucial part of the industrial race is in advanced packaging—the realm where multiple chips, HBM memory, and interconnects are integrated within a single module. In this context, UBS has released an analysis that could set the tone for the coming years: TSMC is allegedly accelerating the development of CoPoS, a panel-based packaging technology, to compete with EMIB-T, Intel’s solution for large-scale AI-oriented packaging.
It’s important to clarify from the beginning. What’s on the table isn’t an official announcement from TSMC setting a public mass production date for CoPoS but rather UBS’s interpretation based on “industry feedback,” suggesting a potential production start in 2028. TSMC publicly acknowledges ongoing development of CoPoS in employment postings and maintains an active discourse on its 3DFabric platform and CoWoS. However, official sources have not yet detailed a complete commercial timeline for CoPoS.
Why Advanced Packaging Has Become the New Battlefront
For years, the market’s focus was almost entirely on lithography processes. That focus has now shifted. The growth of AI and HPC chips has reached a point where packaging is as important as silicon because it determines how many chiplets, HBM memory, and bandwidth can fit within a single module. Intel emphasizes this clearly in its foundry discourse: its official materials present EMIB-T as a technology designed for “ultra-large form factor” devices, with more than six times the reticle size today, over eight times this year, and more than twelve times in 2028.
Meanwhile, TSMC continues to present CoWoS as a core component of its 3DFabric offering for AI and supercomputing. The company describes CoWoS as its reference platform for integrating logic and HBM on silicon interposers. On its corporate website, TSMC maintains CoWoS, SoIC, and SoW as the visible pillars of its advanced packaging roadmap. Notably, CoPoS appears as the logical next step: shifting some of that integration from wafer-scale formats to larger rectangular panels to optimize surface area and potentially improve packaging economics.
This shift isn’t minor. The physical limits of circular wafers start to matter more as encapsulated modules grow larger by stacking multiple logic dies and memory matrices. UBS and other industry analysts suggest panel-level packaging could ease some of that pressure, increase usable surface area, and reduce costs compared to wafer-based solutions. This idea has been around for a while, but it’s gaining urgency due to the increasing size of AI chips.
What Is Confirmed and What Is Still Analyst Expectation
It’s important to distinguish between confirmed facts and assumptions. It is confirmed that TSMC is working on CoPoS: a job posting explicitly references “advanced panel level packaging development for CoPoS technology.” This proves the project exists and is not just market speculation. It’s also confirmed that TSMC continues investing in its advanced packaging ecosystem, with its 2026 Technology Symposium highlighting 3DFabric, CoWoS, SoIC, and SoW.
However, TSMC has not officially confirmed a specific mass production date in 2028. That estimate appears in market analyses and UBS’s interpretation but not in the company’s official statements. The potential partnership between CoPoS and a future NVIDIA generation, like Feynman, also remains speculative at this stage, based on industry forecasts rather than official roadmaps from NVIDIA.
Similarly, with Intel, the situation is somewhat different but related. The company is much more aggressive in promoting EMIB-T. In March, Intel described EMIB-T as its solution for ultra-large encapsulations, combining EMIB advantages with TSVs for better power delivery and interconnection, scaling beyond 12 times reticle size by 2028. However, there’s no official, publicly confirmed date for “mass production” of EMIB-T in H2 2027 or 2028. That timeframe appears in analyst reports and financial media but has not been formally announced by Intel.
Intel Gains Traction, Changing the Pressure on TSMC
UBS’s hypothesis isn’t formed in a vacuum. Recently, there has been increased industry chatter about Intel Foundry and its advanced packaging business. TrendForce indicates Intel is gaining ground over TSMC in AI packaging, while Google and Amazon are exploring options based on EMIB. Financial outlets have also reported discussions with hyperscalers interested in alternatives to CoWoS saturation. While not all these developments are finalized or officially confirmed, they reflect a clear trend: Intel no longer wants to be a secondary player in encapsulation but aims to use EMIB and EMIB-T as real competitive leverage.
This is significant because TSMC leads the advanced packaging arena for AI; however, it faces a clear challenge: the demand for CoWoS has been stretching its capacity for some time. As such, any alternative enabling larger packages or different scalability has strategic value. If Intel successfully convinces more clients of its competitiveness for massive AI packages, TSMC may be driven to accelerate transitioning from CoWoS to solutions like CoPoS.
In essence, TSMC’s challenge isn’t just technical—it’s also commercial and geopolitical. Intel aims to position itself as an American-owned alternative with unique packaging technology, while TSMC remains the industry leader. In this context, panel-level packaging could serve as a way for TSMC to defend its leadership, gain area flexibility, and prepare for the next wave of AI chips demanding even greater integration, more HBM, and larger modules.
The Core Issue: AI Is Moving Packaging to the Center of Business
The most critical insight may not lie solely in CoPoS or EMIB-T individually but in what their combined development reveals. Packaging has shifted from a secondary, almost invisible step to one of the most significant bottlenecks and differentiators in AI. From this point forward, those who master the physical integration of multiple dies, memory, and power delivery will hold a competitive advantage—not just in cost but also in performance, size, and scalability.
Hence, UBS’s report deserves attention, even if some projections remain speculative. It underscores a broader reality: TSMC and Intel are not just competing for nodes or customers but are vying to define the industrial architecture of AI’s grand package in the second half of this decade. The next major leap may not originate from wafers but from panels.
Frequently Asked Questions
What is CoPoS, and how does it differ from CoWoS?
CoPoS stands for Chip on Panel on Substrate and represents an evolution toward panel-based packaging on larger rectangular substrates, compared to CoWoS, which is TSMC’s platform based on Chip on Wafer on Substrate and silicon interposers. The key difference lies in the physical support structure and the potential for increased surface area to accommodate larger packages.
Has TSMC officially confirmed that CoPoS will enter mass production in 2028?
Not yet, based on reviewed sources. It’s confirmed that TSMC is developing CoPoS and actively working on panel-level packaging, but the 2028 date is primarily from market analyses and analyst notes like UBS, not official company communication.
What is EMIB-T, and why is it a concern for TSMC?
EMIB-T is Intel’s evolution of its EMIB technology for ultra-large packages, adding TSVs in the bridge to improve power and interconnects. Intel describes it as a scalable solution expected to surpass 8 times reticle size this year and over 12 times by 2028, highly relevant for massive AI modules.
Is NVIDIA confirmed to use CoPoS in upcoming products like Feynman?
No. The association appears in market analyses and commentary but has not been officially confirmed by NVIDIA through a public roadmap. For now, it remains a hypothesis rather than a confirmed plan.