For months, the dominant narrative about artificial intelligence data centers has been told in kilowatts: lack of grid, lack of substations, lack of permits, lack of water. But in 2026, a more uncomfortable idea for the industry begins to take hold: even when energy is available, the business can get stuck due to an even more “tiny” yet decisive bottleneck: the ability to manufacture and package advanced chips.
This is the argument gaining traction in the industry: that TSMC, the world’s leading contract manufacturer, has effectively become the bottleneck for AI expansion—not due to geopolitics, but because of industrial physics and investment cycles.
The problem: runaway demand and an unforgiving timeline
Building semiconductor fabs and expanding advanced packaging capabilities isn’t like adding servers to a rack. Talking about new real capacity means talking years. According to analysis, part of the current imbalance has a very specific root: TSMC’s capital expenditure (CapEx) remained relatively contained in the years immediately following the surge of generative AI, which today results in waiting lines, rationed orders, and long-term planning by major buyers.
In this context, TSMC has responded… but the calendar remains the calendar. The company has announced it will increase its CapEx for 2026 to a range of $52 billion–$56 billion, a significant jump that the market interprets as a direct response to the appetite for AI chips.
Important nuance: this investment doesn’t “unlock” 2026 overnight. New capacity takes time to come online, and much of the value depends on who secures capacity first and under what commitments.
It’s not just about manufacturing: packaging also matters (and it hurts)
Even if silicon comes off the wafer, another critical ingredient is missing: advanced packaging. The AI supply chain increasingly relies on techniques like CoWoS and other variants, because modern accelerators are, in practice, “systems” within a single package (chiplets, HBM, interposers, etc.). That’s where bottlenecks are evident.
The market consensus is clear: advanced packaging has become the second major bottleneck of the boom, with the direct consequence that having a design or clients isn’t enough—securing a slot in the packaging line is essential.
Why is TSMC acting this way: rational prudence… and transferred risk
From TSMC’s perspective, caution isn’t a whim: semiconductor CapEx is a high-risk bet. If the market cools, depreciation stays. But for hyperscalers (and for anyone monetizing AI at scale), the risk manifests in something less visible but potentially more costly: lost revenue because demand exists, but there aren’t enough chips to meet it.
This marks an important shift in perspective: the “cost” is no longer just price per GPU or electricity bill, but lost business opportunities due to lack of availability.
The uncomfortable debate: diversify or pay the toll?
The strategic conclusion increasingly implied in the sector is almost inevitable: if the world wants to ease the bottleneck, it needs real competition in manufacturing and, above all, in the manufacturing+packaging ecosystem that today TSMC dominates. But diversification also comes with a cost: migrating designs, validating processes, and assuming risks related to performance, timelines, and reliability.
In other words, the market is caught between two risks:
- Concentration risk: reliance on a single “cap” of capacity and accepting rationing (and its economic consequences).
- Transition risk: opening a second route (Intel Foundry, Samsung, etc.) and paying the technical and operational toll.
What makes 2026 particularly interesting is that the debate ceases to be purely theoretical. With rising investment plans and the equipment industry celebrating this shift, the implicit message is that the AI boom isn’t stalled by lack of ideas or capital, but by the actual speed at which the world can produce the “atoms” of computing.
Frequently Asked Questions
Why is there a “lack of AI” if tech giants are investing billions?
Because demand for deployment of inference and services is growing, but the supply chain (wafer + advanced packaging + HBM memory) isn’t growing at the same pace.
What is advanced packaging and why is it so critical for AI?
It’s the set of techniques to integrate chiplets and high-bandwidth memory into a single package. In modern accelerators, performance depends as much on packaging as on the chip itself.
When might TSMC’s bottleneck ease?
Industry typically talks in multi-year horizons: CapEx helps, but new capacity takes time to come online, and much of the bottleneck still lies in packaging.
What can hyperscalers do to reduce dependency?
Secure capacity through long-term contracts, optimize models to use less hardware per token, and simultaneously explore second sources (with the validation costs that entails).
via: stratechery