TSMC is preparing for the second half of 2026 A16, their first technology that combines nanosheet transistors with Super Power Rail (SPR), a power delivery system from the backside of the chip. This advancement aims to resolve one of the challenges that emerge when further reducing manufacturing processes: electrical lines and signals compete for increasingly limited space. The company also assures that its implementation maintains gate density, design area, and device flexibility comparable to its conventional technology, a particularly relevant point compared to other backside power delivery approaches.
The key points of TSMC A16 in 30 seconds
- A16 introduces Super Power Rail, shifting the power network to the backside of the chip.
- TSMC claims it maintains comparable gate density, area, and flexibility to traditional front-side power.
- Compared to N2P, it promises 8-10% higher speed or 15-20% lower power consumption, depending on the scenario.
- Density could increase by up to 1.10 times.
- Intel already has PowerVia in 18A, so competition also centers on how to integrate this technology without complicating design.
For decades, electricity and data have essentially traveled along the same side of a processor. Over transistors, different metal layers are built to carry signals and distribute power.
This system has worked as manufacturers gradually reduced transistor sizes, but each new generation makes it more challenging to maintain.
Connections become smaller and their resistance increases. At the same time, artificial intelligence (AI) processors and high-performance computing (HPC) require transmitting enormous amounts of current to billions of transistors.
The result is a seemingly simple problem: more and more things are trying to pass through less space.
The industry is responding by flipping the chip.
Why TSMC, Intel, and Samsung want to power chips from the back
The concept of Backside Power Delivery Network (BSPDN) involves separating two functions that traditionally share the metal layers above transistors.
Signals remain on the front.
Electricity passes from the back.
This enables reserving front connections mainly for communications and creating an independent electrical network on the backside.
One advantage is reducing the so-called IR drop, the voltage drop due to the electrical resistance of interconnections.
This issue becomes more critical as the current requirements of processors increase. AI GPUs or ASICs can experience rapid fluctuations in power consumption and require stable power delivery at the intended operating frequencies.
Intel has been working on this concept with PowerVia. In early test chips, the company achieved over 90% cell utilization, more than 30% improvement in voltage drop, and approximately 6% gain in frequency.
PowerVia is part of Intel 18A alongside RibbonFET transistors, Intel’s Gate-All-Around (GAA) architecture.
TSMC is now pursuing its own path with A16.
| Technology | Backside power | Transistor | Differentiation point |
|---|---|---|---|
| TSMC A16 | Super Power Rail | Nanosheet | Maintain gate density, design area, and flexibility |
| Intel 18A | PowerVia | RibbonFET | Backside power integrated into the 18A family |
| Samsung 2 nm | BSPDN in development | GAA/MBCFET | Gradual deployment in advanced process families |
A direct comparison cannot simply claim that one technology is superior to others. Intel was a pioneer in demonstrating PowerVia on silicon and has integrated it into 18A. What’s new about TSMC’s approach is how they plan to introduce backside power while preserving existing design characteristics.
Super Power Rail: the differentiator TSMC aims to exploit
TSMC terms its technology Super Power Rail.
A16 shifts power delivery to the backside and uses dedicated vertical connections to bring it closer to the transistors.
This frees up interconnection resources on the front and allows more space for signal transmission.
Up to this point, the principle is similar to other backside power implementations.
TSMC’s highlighted difference lies in its contact scheme.
The company states that its technology enables maintaining the same gate density, layout footprint, and device width flexibility as a traditional front-side power design. TSMC presents this as an industry-first feature.
While this may seem like a minor detail, it has significant implications for designers.
A new manufacturing process is not only about shrinking transistors. Around each node, there is an enormous set of cell libraries, design rules, EDA automation tools, and intellectual property that chip manufacturers need to adapt and validate.
Radically changing cell structures might require modifying part of that work.
Therefore, reducing the modifications needed to adopt backside power can ease the transition to the new process.
TSMC is aiming to turn that compatibility into one of the main arguments for A16.
A16 doesn’t simply replace N2
It’s also important to clarify the naming, as TSMC has moved beyond just nanometers to identify its most advanced processes.
The family starts with N2, the 2-nanometer process whose volume production began in Q4 2025.
Next is N2P, an evolution aimed at improving performance and efficiency.
A16 builds on the technology base of this generation but incorporates Super Power Rail and is especially targeted at HPC (High-Performance Computing) applications with complex signal routing and densely packed power networks.
According to official TSMC data, A16 will offer compared to N2P:
| Comparison A16 vs N2P | Promised improvement |
|---|---|
| Same voltage speed | +8-10% |
| Same performance, lower power | -15-20% |
| Chip density | Up to 1.10× |
| Expected mass production | Second half of 2026 |
These are TSMC’s stated targets and do not necessarily mean a commercial processor will be 10% faster and 20% more power-efficient simultaneously. They represent different operating points used to compare technologies.
Intel arrived first with PowerVia
Labeling A16 simply as a technology that puts TSMC “ahead of Intel” would be an oversimplification.
Intel has a temporal advantage in backside power.
The company introduced PowerVia results in 2023 and demonstrated the technology with an E-Core specifically fabricated to test its functionality before combining it with RibbonFET.
Those tests already showed frequency improvements and voltage drop reduction. Intel also had to solve new challenges related to manufacturing, temperature, and silicon diagnostics, as implementing connections on both sides significantly alters chip structure.
Intel’s 18A currently combines both technologies.
The company explains that moving the electrical network to the backside frees up space for signals, enables more direct connections, and reduces worst-case dynamic voltage drop compared to front-side power networks.
Thus, the competition between Intel and TSMC is no longer about who invented backside power first but about who can integrate it with better density, performance, design simplicity, manufacturing yield, and cost.
That’s where TSMC’s Super Power Rail aims to stand out.
AI makes powering chips almost as important as manufacturing transistors
It’s no coincidence that TSMC presents A16 as a technology particularly suited for data centers.
AI accelerators rapidly increase transistor counts, system sizes, and power consumption.
Each new generation needs to move more data and transmit higher currents.
This makes the internal power network of the chip part of the performance equation. A faster transistor is of little use if interconnections cannot carry signals adequately or if power drops excessively.
Backside power aims to address both issues simultaneously: it leaves more space at the front for signals and creates a more direct electrical route behind.
A16 also marks another shift in the semiconductor race. For years, much attention focused on shrinking transistor sizes. The next stage involves innovation around the transistors themselves: backside power, advanced packaging, chiplets, 3D interconnects, and new ways to integrate memory.
TSMC expects A16 to be ready for production in H2 2026. That will be when the most critical part of the comparison begins: to see which customers adopt Super Power Rail and what benefits it ultimately delivers when moving from process numbers to large HPC and AI commercial chips.
Frequently Asked Questions
What is TSMC A16?
A16 is an advanced manufacturing technology by TSMC that combines nanosheet transistors with Super Power Rail, their backside power delivery system. It is mainly targeted at HPC products with particularly complex electrical and signal networks.
What advantages does A16 offer over N2P?
TSMC claims an 8-10% increase in speed at the same voltage, a 15-20% reduction in power consumption at the same performance, and up to 1.10 times the chip density.
What is the difference between Super Power Rail and PowerVia?
Both technologies move power distribution to the backside of the chip. Intel was a pioneer with PowerVia, while TSMC emphasizes that its A16 contact scheme allows maintaining gate density, layout footprint, and device width flexibility comparable to traditional front-side power designs.
When will TSMC A16 be available?
TSMC plans to have A16 ready for production in the second half of 2026.
