For the second half of 2026, TSMC is preparing A16, its first technology that combines nanosheet transistors with Super Power Rail (SPR), a system that delivers power from the backside of the chip. The advance tackles one of the problems that shows up as manufacturing processes keep shrinking: electrical lines and signals compete for ever tighter space. The company also says its implementation keeps gate density, design area, and device flexibility comparable to its conventional technology, a point that stands out against other backside power delivery approaches.
TSMC A16 in 30 seconds
- A16 introduces Super Power Rail, moving the power network to the backside of the chip.
- TSMC says it keeps gate density, area, and flexibility comparable to traditional front-side power.
- Against N2P, it promises 8-10% higher speed or 15-20% lower power, depending on the scenario.
- Density could rise up to 1.10 times.
- Intel already has PowerVia in 18A, so the competition is also about how to integrate this without complicating design.
For decades, electricity and data have mostly traveled on the same side of a processor. On top of the transistors, different metal layers carry signals and distribute power.
That has worked as manufacturers gradually shrank transistors, but each new generation makes it harder to sustain.
Connections get smaller and their resistance rises. At the same time, AI processors and high-performance computing (HPC) have to push enormous currents to billions of transistors.
The result is a deceptively simple problem: more and more things are trying to pass through less space.
The industry’s answer is to flip the chip.
Why TSMC, Intel, and Samsung want to power chips from the back
The idea of a Backside Power Delivery Network (BSPDN) is to separate two functions that traditionally share the metal layers above the transistors.
Signals stay on the front.
Power comes from the back.
That reserves the front connections mainly for communications and builds an independent power network on the backside.
One benefit is cutting the so-called IR drop, the voltage drop caused by the electrical resistance of the interconnections.
That gets more critical as processors’ current requirements climb. AI GPUs or ASICs can swing rapidly in power draw and need stable delivery at the intended operating frequencies.
Intel has been working on this with PowerVia. In early test chips, it reached over 90% cell utilization, more than 30% improvement in voltage drop, and about 6% gain in frequency.
PowerVia is part of Intel 18A alongside RibbonFET transistors, Intel’s Gate-All-Around (GAA) architecture.
TSMC is now taking its own route with A16.
| Technology | Backside power | Transistor | Differentiation point |
|---|---|---|---|
| TSMC A16 | Super Power Rail | Nanosheet | Maintain gate density, design area, and flexibility |
| Intel 18A | PowerVia | RibbonFET | Backside power integrated into the 18A family |
| Samsung 2 nm | BSPDN in development | GAA/MBCFET | Gradual deployment in advanced process families |
You can’t just say one technology is better than the others. Intel was a pioneer in demonstrating PowerVia on silicon and has folded it into 18A. What’s new in TSMC’s approach is how it plans to bring in backside power while keeping the existing design characteristics.
Super Power Rail: the edge TSMC wants to press
TSMC calls its technology Super Power Rail.
A16 moves power delivery to the backside and uses dedicated vertical connections to bring it closer to the transistors.
That frees up interconnect resources on the front and leaves more room for signals.
Up to here, the principle is similar to other backside power implementations.
TSMC’s highlighted difference is in its contact scheme.
The company says its technology keeps the same gate density, layout footprint, and device-width flexibility as a traditional front-side power design. TSMC presents this as an industry first.
That may sound like a small detail, but it means a lot for designers.
A new process isn’t only about shrinking transistors. Around each node sits a huge set of cell libraries, design rules, EDA automation tools, and intellectual property that chipmakers have to adapt and validate.
Radically changing the cell structures might mean redoing part of that work.
So cutting the changes needed to adopt backside power can smooth the move to the new process.
TSMC wants to turn that compatibility into one of A16’s main selling points.
A16 doesn’t simply replace N2
The naming is worth clarifying, since TSMC has moved past just nanometers to label its most advanced processes.
The family starts with N2, the 2-nanometer process whose volume production began in Q4 2025.
Next is N2P, an evolution aimed at better performance and efficiency.
A16 builds on this generation’s technology base but adds Super Power Rail, and it’s aimed especially at HPC (High-Performance Computing) applications with complex signal routing and dense power networks.
Per official TSMC data, A16 offers, compared to N2P:
| A16 vs N2P | Promised improvement |
|---|---|
| Same voltage, speed | +8-10% |
| Same performance, lower power | -15-20% |
| Chip density | Up to 1.10× |
| Expected mass production | Second half of 2026 |
These are TSMC’s stated targets and don’t necessarily mean a commercial processor will be 10% faster and 20% more power-efficient at the same time. They’re different operating points used to compare technologies.
Intel got there first with PowerVia
Calling A16 simply a technology that puts TSMC “ahead of Intel” would oversimplify.
Intel has a head start on backside power.
It presented PowerVia results in 2023 and demonstrated the technology with an E-Core built specifically to test it before combining it with RibbonFET.
Those tests already showed frequency gains and voltage-drop reduction. Intel also had to solve new challenges around manufacturing, temperature, and silicon diagnostics, since putting connections on both sides changes the chip structure significantly.
Intel 18A now combines both technologies.
The company explains that moving the power network to the backside frees up space for signals, allows more direct connections, and cuts worst-case dynamic voltage drop compared with front-side power networks.
So the Intel-TSMC competition is no longer about who invented backside power first, but about who can integrate it with better density, performance, design simplicity, manufacturing yield, and cost.
That’s where TSMC’s Super Power Rail wants to stand out.
AI makes powering chips almost as important as building transistors
It’s no accident that TSMC presents A16 as a technology well suited to data centers.
AI accelerators keep raising transistor counts, system sizes, and power draw.
Each new generation has to move more data and push higher currents.
That makes the chip’s internal power network part of the performance equation. A faster transistor helps little if the interconnections can’t carry signals well or the power drops too much.
Backside power aims to tackle both at once: it leaves more room at the front for signals and creates a more direct electrical route behind.
A16 also marks another shift in the semiconductor race. For years, most of the attention went to shrinking transistors. The next stage is innovation around the transistors themselves: backside power, advanced packaging, chiplets, 3D interconnects, and new ways to integrate memory.
TSMC expects A16 to be ready for production in H2 2026. That’s when the most important part of the comparison begins: seeing which customers adopt Super Power Rail and what it actually delivers once it moves from process numbers to large HPC and AI commercial chips.
Frequently Asked Questions
What is TSMC A16?
A16 is an advanced TSMC manufacturing technology that combines nanosheet transistors with Super Power Rail, its backside power delivery system. It’s aimed mainly at HPC products with especially complex electrical and signal networks.
What does A16 offer over N2P?
TSMC claims an 8-10% speed increase at the same voltage, a 15-20% cut in power at the same performance, and up to 1.10 times the chip density.
What’s the difference between Super Power Rail and PowerVia?
Both move power distribution to the backside of the chip. Intel was the pioneer with PowerVia, while TSMC emphasizes that its A16 contact scheme keeps gate density, layout footprint, and device-width flexibility comparable to traditional front-side power designs.
When will TSMC A16 be available?
TSMC plans to have A16 ready for production in the second half of 2026.
