The debate over who will lead the next generation of artificial intelligence chips is no longer limited to nanometers. The focus has shifted to advanced packaging, HBM memory, substrates, interposers, and the actual capacity to manufacture millions of complex accelerators without breaking the supply chain. In this arena, TSMC continues to hold a significant advantage that’s difficult to erode in the short term.
A Citi report cited by Wccftech states that TSMC does not face an immediate significant threat from Intel in AI chips, despite growing interest in EMIB-T, the advanced packaging technology that Intel is promoting for high-performance accelerators. The reason isn’t a lack of technology on Intel’s part but rather that their ability to scale depends on a less visible component for the general public: ABF substrates and the maturity of the ecosystem that produces them.
EMIB-T is promising, but having a good architecture isn’t enough
Intel’s EMIB isn’t an improvised technology. Its approach involves inserting small silicon bridges within an organic substrate to connect chiplets without relying on a full silicon interposer, as is common in many traditional 2.5D configurations. In theory, this reduces costs and increases flexibility for complex packages.
The evolution to EMIB-T adds TSV vias within the silicon bridge itself to improve vertical power delivery and signal routing. Intel Foundry explains in their documentation that EMIB-T responds to increased demand for HBM and the need to deliver power with less electrical noise — critical in AI accelerators with many chiplets and high-bandwidth memory.
The issue, according to Citi’s view, lies in scaled manufacturing. EMIB-T depends on ABF substrates, a vital material in advanced packaging. If ABF suppliers can’t increase capacity, improve performance, and maintain quality at the volumes needed, Intel will have an intriguing technology but one limited by the same sector-wide reality: no one buys roadmaps, only finished, validated, and timely finished packages.
Comparison with TSMC is unavoidable. CoWoS, the Taiwanese company’s advanced packaging platform, is already deeply integrated into the AI ecosystem. NVIDIA, AMD, Broadcom, Google, and other accelerator designers rely on this type of packaging to combine large compute dies with HBM memory. CoWoS isn’t perfect or unlimited, but it’s in mass production, has reference clients, and benefits from a mature supply chain.
Intel may attract interest from clients seeking alternatives due to CoWoS saturation. Google, Amazon, and other hyperscalers have clear incentives to diversify suppliers and avoid bottlenecks. However, moving from discussions, tape-outs, or prototype vehicles to high-volume production is another story. In semiconductors, a positive technical test doesn’t guarantee widespread adoption.
TSMC expands in CoWoS, SoIC, and larger systems
TSMC is responding to AI demands by expanding capacity in several directions. According to TrendForce data, CoWoS capacity could reach between 115,000 and 140,000 wafers per month by late 2026, rising to around 170,000 in 2027. The expansion will be particularly focused in Tainan and Chiayi, at a scale much larger than previous cycles.
The company has also outlined a much more ambitious roadmap for the coming years. At the Taiwan Technology Symposium 2026, TSMC indicated that demand for wafers for AI accelerators will grow 11-fold between 2022 and 2026, and raised its global semiconductor market forecast to over $1.5 trillion by 2030. Simultaneously, it projects CoWoS capacity will grow at a CAGR exceeding 80% from 2022 to 2027.
The most notable detail concerns the evolution of packaging itself. TSMC is working on versions of CoWoS capable of integrating more HBM memory. Reports after the symposium point to a 14-reticle version with up to 20 stacks of HBM in 2028 and designs with up to 24 stacks in 2029. Additionally, the company is advancing in SoIC, silicon photonics, and System on Wafer technologies aimed at closer integration of memory, compute, and interconnect within the same system.
| Technology | Role in AI chips | Competitive Status |
|---|---|---|
| TSMC CoWoS | 2.5D integration of compute and HBM | In mass production with strong demand |
| Intel EMIB-T | Silicon bridges with TSV in organic substrate | Promising but ecosystem-dependent |
| TSMC SoIC | 3D chip-on-chip stacking | Expanding for future generations |
| CoPoS / Panel-level | Large packages at lower cost | Still maturing |
| System on Wafer | Wafer-scale integration | Roadmap to 2029 |
This combination explains why Citi considers TSMC’s position to remain strong. Their advantage isn’t based on a single technique but on a comprehensive set: advanced nodes, packaging, customers, suppliers, manufacturing expertise, performance, capacity, and a roadmap aligned with AI model evolution.
Intel has an opportunity, but the window won’t be easy
Intel Foundry needs to turn its technical advancements into external business. EMIB-T could be an attractive route because many clients want to reduce dependence on TSMC and secure additional capacity for AI ASICs. Additionally, Intel has a compelling industry narrative: U.S. manufacturing, advanced packaging, Foveros, EMIB, PowerVia, and the 18A process.
However, Citi emphasizes an important nuance regarding Intel’s 18A. A major customer’s tape-out or process evaluation doesn’t guarantee mass production. For AI and HPC chips, designs slated for the 2027–2028 market are often already very advanced or finalized. Changing foundries, nodes, or packaging technologies at that stage can be costly and risky.
This doesn’t eliminate Intel’s potential. The company can win specific projects, especially if it offers capacity where TSMC is saturated or if certain clients want a second source. It might also have more options with new designs tailored from the ground up for EMIB-T. But it’s unrealistic to expect Intel to swiftly displace TSMC at the core of high-volume AI accelerators.
The reasons are industry-wide, not just technological. AI has pushed multiple supply chain layers to their limits: HBM, CoWoS, substrates, interposers, testing equipment, assembly, materials, and power capacity in data centers. Within this context, trust plays a crucial role. A client committing billions to accelerators isn’t just looking at theoretical performance—they consider availability, yield, support, schedules, HBM compatibility, prior experience, and execution risk.
This is why TSMC remains so resilient. Its dominance isn’t invulnerable but is difficult to challenge in the short term. Intel could pose a serious alternative if it manages to scale EMIB-T, secure ABF supply, demonstrate reliable production, and convince clients of volume capability. Until then, TSMC’s AI leadership will rest on more than just its reputation: a complete manufacturing chain already producing the chips the market demands.
The race in advanced packaging is just beginning. CoWoS won’t be the only answer forever, and AI architectures will require larger packages, more memory, and better interconnects. For now, TSMC’s advantage isn’t merely based on a promising technical announcement but on years of mass production, mature suppliers, and available capacity—things hardest to build.
FAQs
What is EMIB-T?
EMIB-T is an evolution of Intel’s EMIB packaging technology. It adds TSV vias within the silicon bridge to improve vertical power delivery and signal routing in advanced packages with chiplets and HBM memory.
Why does Citi believe Intel doesn’t threaten TSMC yet?
Because EMIB-T’s success depends on scaling the ABF substrate ecosystem and turning the technology into mass production. TSMC already has a mature CoWoS platform and a well-established supply chain for AI chips.
What is CoWoS?
CoWoS is TSMC’s advanced packaging technology enabling the integration of large compute dies and HBM memory within a single package via interposers or related solutions, critical for AI accelerators.
Can Intel win AI customers with EMIB-T?
Yes, especially if clients seek to diversify suppliers or address CoWoS saturation. However, securing specific projects doesn’t mean a swift displacement of TSMC in high-volume production.
via: wccftech