TSMC has confirmed that its 2-nanometer process is progressing much faster than the previous generation: during its second year, it has accumulated four times more tape-outs than the 3 nm at the same stage of development. The N2 technology already contributed 3% of wafer revenue in the second quarter of 2026, not the third as some reports indicate, as AI demand accelerates the hiring of advanced capacity.
The key points of TSMC’s 2-nanometer process in 30 seconds
- N2 reports four times as many completed designs as N3 during its second year, although this does not mean four times more chips sold.
- The 2 nm process accounted for 3% of wafer-based revenue in Q2 2026.
- High-performance computing (HPC) contributed 66% of TSMC’s revenue, compared to 22% from mobile devices.
- AMD is already manufacturing its upcoming EPYC Venice chips on N2; chips attributed to Google, Apple, or Qualcomm are still unconfirmed officially.
This info was shared by Kevin Zhang, Senior Vice President and Deputy Director of TSMC Operations, during the Technology Symposium held on 07/03/2026 in Yokohama. The company expects the 2 nm family to see wider and more sustained adoption than the 3 nm, with applications in mobile devices, data center processors, AI accelerators, and other high-performance systems.
The comparison measures designer interest but does not indicate that TSMC is manufacturing four times as many wafers nor that it will quadruple N3 revenue. Between design completion and market launch, steps include mask fabrication, initial wafers, testing, performance improvements, encapsulation, and preparation for commercial release.
Four times more tape-outs doesn’t mean four times more chips
A tape-out is when a manufacturer finalizes a chip design and sends the definitive version to the foundry for production setup. Reaching this stage indicates that the customer has invested time and money in adapting the product to the process, though errors or changes can still occur before mass production.
The number of tape-outs serves as a leading indicator of adoption. More projects reaching this phase suggests a larger potential pipeline of future products for TSMC. Not all designs will be equal in size, volume, or profitability: a small mobile chip and a large data center processor both count as one design, despite requiring vastly different amounts of silicon.
| Indicator | What it represents | What it does not prove |
|---|---|---|
| Tape-out | Design finalized and sent to manufacturing | Product already available in the market |
| Four times as many designs | Higher number of projects compared to N3 | Four times as many wafers |
| Revenue from N2 | Factored production revenue during the quarter | Sales of consumer devices |
| Contracted capacity | Expected customer demand | Final utilization rate |
| Manufacturing yield | Percentage of usable chips per wafer | Real-world product performance |
N2 is the first TSMC process to use nanosheet transistors with a gate-all-around (GAA) structure. Compared to N3E, the manufacturer announces a speed improvement of between 10% and 15%, maintaining power consumption, or an energy reduction of 25% to 30% at the same performance level. Chip density could increase by more than 1.15 times, though actual results depend on the design and mix of logic, memory, and interconnects.
TSMC began volume production of N2 in Q4 2025. Just two quarters later, the process contributed 3% of wafer-based revenue for the company, based on the second quarter of 2026 figures, which closed on June 30; the third quarter was just beginning when this info was published.
| TSMC Technology Revenue (Q2 2026) | |
|---|---|
| 2 nm | 3% |
| 3 nm | 30% |
| 5 nm | 33% |
| 7 nm | 11% |
| 7 nm or below technologies | 77% |
It is normal to see revenue contributions before the public launch of many products. TSMC invoices wafer manufacturing to its customers before processors are encapsulated, integrated into servers or phones, and reach retail stores.
AI now takes the space previously dominated by mobile devices
The growth of N2 coincides with a shift in TSMC’s business mix. High-performance computing (HPC), which includes data center processors and AI accelerators, increased by 20% quarter-over-quarter and already accounts for 66% of revenue. Mobile devices declined by 4% and represent 22% of the mix.
| Platform | Share of Q2 Revenue |
|---|---|
| High-performance computing | 66% |
| Smartphones | 22% |
| Internet of Things | 5% |
| Automotive | 4% |
| Consumer electronics | 1% |
This distribution helps explain why future data center accelerators and processors could consume a significant portion of 2 nm capacity. These are large chips, with high prices, and they require advanced packaging, high-bandwidth memory, and high-performance networks.
The first publicly confirmed customer product on N2 is AMD. In May, AMD announced it was increasing production of Venice, its next-generation EPYC server processors. AMD describes it as the first HPC product to reach this stage with TSMC’s 2 nm process and plans to use it in its upcoming family, Verona.
TSMC typically does not disclose all customers or products in production. Nor has it confirmed that Google’s Tensor G6 is the first 2 nm mobile processor, nor that Apple’s rumored A20 Pro or future Snapdragon and Dimensity generations will use N2 or N2P. These names are based on leaks and supply chain reports, not official announcements from the companies.
There is also no confirmation that Apple will drop 2 nm after two generations to avoid shortages. Moving to A14—sometimes called “1.4 nm” informally—would be part of normal chip evolution if the company decided to do so, but TSMC has not announced capacity allocations or preferences among clients.
The foundry confirms that AI-related demand remains very strong. Its CEO, C. C. Wei, explained that AI agents are also increasing data center CPU needs, alongside accelerators. TSMC manufactures chips for customers with x86, Arm, and RISC-V architectures, thus benefiting regardless of processor choice.
The company raised its capital expenditure forecast for 2026 to between $60 billion and $64 billion. Around 70-80% will go to advanced processes, while 10-20% will cover encapsulation, testing, masks, and other areas.
Starting a new technology also incurs costs. TSMC expects that the rapid ramp-up of N2 will reduce its gross margin by 3 to 4 percentage points in the second half of the year. Early phases involve equipment depreciation, lower productivity, and learning expenses until wafer yields improve.
N2P, N2X, and N2U will extend the commercial life of 2 nm
N2 will not be a single process but the beginning of a family with variants tailored to different needs. The strategy mirrors TSMC’s approach with N5 and N3: maintaining compatible design rules where possible and improving performance, power, or density without forcing a complete redesign.
| Process | Orientation | Announced Improvements |
|---|---|---|
| N2 | Mobile, AI, and HPC | Up to 15% faster or 30% less power compared to N3E |
| N2P | Compatible evolution of N2 | Approximately 5% more performance than N2 |
| N2X | Maximum performance | Up to 10% additional via high-speed cells and devices |
| N2U | Balanced option for mobile and HPC | Between 3-4% faster or 8-10% lower power than N2P |
| A16 | HPC with back-side power | Between 8-10% faster than N2P |
| A14 | Second-generation nanosheets | Up to 15% faster or 30% less power than N2 |
N2P maintains N2 design rules and adds about 5% performance improvement. TSMC believes it will capture most of the family’s adoption, as it allows transferring existing IP and blocks with minimal changes. Production is expected in the second half of 2026.
N2X targets chips that prioritize frequency and can handle higher power. It combines high-performance cells with fast devices that can be inserted only into critical paths.
N2U, arriving in 2028, offers a more moderate improvement over N2P. Its goal is to leverage the maturity and productivity levels already achieved, providing a practical option for products seeking efficiency and predictable costs without immediately moving to A14.
For large AI workloads, TSMC is also preparing A16, which adds back-side power delivery. This technology frees up space on the front, reduces voltage drops in densely wired power networks, and supports high-performance AI chips.
The increasing number of tape-outs indicates that customers are willing to bear the costs of designing for N2. Commercial deployment will occur once these projects move to mass production, achieve good yields, and see market demand.
Currently, confirmed data shows adoption faster than N3, with strong revenue growth and capacity increasingly conditioned by AI infrastructure. There is no evidence that mobile manufacturers have lost access to 2 nm nodes nor details on how TSMC will allocate wafers among Apple, AMD, Nvidia, Google, Qualcomm, or MediaTek.
Frequently Asked Questions
What does it mean that N2 has four times as many tape-outs as N3?
It means that four times as many designs reached the tape-out stage during the second year of the technology. It does not imply four times more chips manufactured or sold.
Did the 2 nm process contribute 3% of revenue in the third quarter?
Which commercial product is already using TSMC’s 2 nm?
AMD has confirmed that its EPYC Venice processors are increasing production on N2. Other mobile products attributed to Google, Apple, Qualcomm, or MediaTek are not officially confirmed yet.
Why might AI limit capacity for mobile devices?
Data center processors and accelerators use large designs that demand increasing volumes. However, TSMC has not announced any capacity removal from smartphone manufacturers or detailed how it will allocate this capacity.
