For years, the semiconductor industry has been seeking ways to continue increasing chip density as transistor scaling becomes ever more challenging. The most well-known approach so far has been advanced packaging: chiplets, stacked memory, interposers, 3D V-Cache, or HBM. But a team from the University of Illinois Urbana-Champaign has demonstrated a different, much deeper route: fabricating multiple layers of silicon transistors directly atop one another within the same chip.
Led by Professor Qing Cao, this advance is based on monolithic 3D integration with single-crystal silicon. Simply put: instead of manufacturing separate chips and joining them later in the package, researchers have built new active circuit layers directly on top of an already completed layer. The initial result is three stacked levels, each with 625 transistors, achieving fabrication yields between 98% and 100%, even in a university cleanroom environment, as reported by Illinois Grainger Engineering.
Published in Nature, this research targets one of current microelectronics’ biggest obsessions: increasing computational capacity, internal communication speed, and energy efficiency without solely relying on making transistors ever smaller.
Stacking chips is not the same as stacking transistors
3D chips already exist in commercial products. HBM stacks memory next to AI accelerators. AMD’s 3D V-Cache places an additional cache layer over the CPU die. Intel uses tile-based architectures and advanced packaging to combine separately fabricated blocks. These techniques have enabled significant jumps, but they still work with complete components fabricated on different wafers and joined afterward.
Monolithic 3D integration proposes something different: each device layer is built directly on top of the previous one during the manufacturing process. This allows for much denser vertical connections, smaller separations between layers, and nanometer-scale alignment. According to Illinois, this approach can offer 10 to 100 times more vertical connection density than conventional TSV-based stacking, which uses vias to connect entire chips or wafers.
The difference is not just academic. In modern processors, much of the power consumption and latency comes from moving data between blocks. If those blocks are closer and more densely connected, the energy required for inter-block communication can be reduced, and internal bandwidth increased. For AI, high-performance computing, cache memory, signal processing, and specialized circuits, this proximity can be highly valuable.
Qing Cao explains it with an easy analogy: today, an SRAM cell requires six transistors on the same plane to store one bit. With vertical integration, these transistors can be distributed across multiple layers. It’s like replacing sprawling urban development with high-rise buildings: the function is the same, but surface area is reduced, and internal communication can be faster.
| Technology | What it stacks | Main limitation |
|---|---|---|
| Chiplets | Complete blocks manufactured separately | Connections less dense than within the die |
| HBM | Memory layers | Very useful, but focused on memory only |
| 3D V-Cache | Cache over CPU die | Stacking after fabrication on an existing chip |
| Monolithic 3D Integration | Layers of transistors within the same chip | Significant thermal and manufacturing challenges |
| Illinois Method | Nanomembranes of single-crystal silicon | Still in research phase |
The thermal barrier that slowed down 3D silicon
The main obstacle to fabricating transistors atop others was temperature. Conventional processes for producing high-quality crystalline silicon and high-performance devices can approach 1,000°C. Such temperatures would damage or degrade underlying layers that are already metallized, as the interconnects and materials used in finished circuits cannot withstand that treatment.
Industry typically limits the maximum temperature for upper layers to around 400°C once the first circuit layer is completed. This margin makes it very difficult to use standard single-crystal silicon for additional layers. Consequently, many earlier attempts turned to alternative materials such as polycrystalline silicon, metal oxides, carbon nanotubes, or 2D semiconductors. However, these materials often face limitations in performance, uniformity, or reliability.
The Illinois team circumvented this barrier with ultrathin nanomembranes of monocrystalline silicon, 10 nanometers or less in thickness. These sheets are extracted from a donor wafer and transferred onto the receiving substrate, which already contains the first circuit layer. The transfer employs a roller laminator, and bonding occurs at 200°C or less—well below industry’s thermal limit for subsequent layers.
Using junctionless transistors is also key. Instead of relying on high-temperature doping processes afterward, the material is pre-doped uniformly before stacking. Since silicon sheets are extremely thin, the transistor gate can effectively control the channel, while parasitic contact resistance is reduced.
Three layers, functional SRAM, and comparable performance
The experimental result goes beyond a visual demonstration. Researchers built three stacked layers, each with 625 transistors, achieving good uniformity and high performance. The output current densities were comparable to standard silicon transistors fabricated on conventional wafers using high-temperature processes, and at least three to four times higher than devices made with alternative materials.
Moreover, the team connected the layers with vertical metal lines and demonstrated 3D logic circuits and functional SRAM cells. This is a critical step toward real-world applications, showing that layers can communicate and form useful circuits, not just stacking semiconductor material.
That said, it’s important not to overstate immediate prospects. This technology will not replace chiplets or advanced packaging tomorrow. Moving toward industrial manufacturing requires solving issues related to scaling, process compatibility, defect control, metallization integration, thermal design, EDA tools, testing, and costs. Illinois notes that efforts are underway to transfer this process to an industrial semiconductor foundry.
The positive sign is that the process seems designed from the outset to be compatible with standard silicon—no exotic materials needed. This could facilitate adoption if larger wafers, additional layers, and more complex designs are demonstrated successfully.
A path for scaling without shrinking everything
Moore’s Law, understood as the sustained increase in transistors per chip, has slowed due to physical and economic factors. Transistors are reaching limits where atomic dimensions, quantum effects, variability, manufacturing costs, and design complexity make each new node more difficult.
Building vertically offers a solution. It does not eliminate the need for transistor improvements but adds an extra dimension. Instead of trying to fit everything on a planar surface, functions can be distributed across layers, interconnections shortened, and density increased without solely relying on lateral shrinking of devices.
For AI, this approach may be particularly beneficial. Modern accelerators are limited by data movement among memory, cache, compute units, and interconnects. If circuits can be integrated vertically with dense connections, more compact and efficient architectures, with memory and logic much closer together, could be designed.
It could also impact SRAM, one of the most critical and costly components in many chips. Cache memory occupies a large portion of CPU and GPU die area. If SRAM cells can be distributed across multiple layers, significant surface area savings could be achieved.
Illinois’s research does not suggest the end of chip stacking. Rather, it opens another avenue that could coexist with chiplets, HBM, advanced packaging, and new architectures. The future likely won’t be a single technique but a combination of 2D scaling, monolithic 3D stacking, system-in-package, and heterogeneous integration.
The key point is that stacking is no longer limited to packaging. It begins to be integrated within the chip itself. If this transition reaches manufacturing, the next step in density growth will not just rely on smaller transistors, but on transistors placed vertically.
Frequently Asked Questions
What have Illinois researchers demonstrated?
They have shown a method to stack three layers of single-crystal silicon transistors directly within the same chip, using ultrathin nanomembranes and a low-temperature process.
How does this differ from chiplets or HBM?
Chiplets and HBM stack or integrate separately fabricated modules. Monolithic 3D integration fabricates new transistor layers directly on top of completed layers.
Why is low temperature important?
Because underlying layers already contain circuitry and metallization. Processes near 1,000°C would damage them, whereas the Illinois method works at 200°C or below.
Will this soon appear in commercial chips?
Not yet. It’s still in the research phase with promising initial results, but translating it to industrial foundries and demonstrating scalability with complex designs is needed.
via: matse.illinois.edu and elchapuzasinformatico