For nearly 60 years, Moore’s Law has been the industry’s compass: every 18–24 months, more transistors per chip, delivering increased power per dollar and per watt. But that virtuous cycle has hit a physical wall. At scales of a few nanometers, quantum effects, leakage currents, and thermal density turn further silicon miniaturization into a game of diminishing returns. The results are visible: frequencies stagnating around 5 GHz, increasingly modest gains per node, and escalating costs and complexity that only a few fabs can sustain.
Meanwhile, as the West refines Silicon FinFETs and GAAFETs and pushes 3D stacking where possible (like HBM memory and advanced packaging), a team from Peking University has demonstrated an alternative route: two-dimensional gate-all-around transistors based on bismuth, integrated monolithically in 3D at low temperatures. Their study, published in Nature Materials, proposes a pair of materials functioning as if designed for each other: Bi₂O₂Se as semiconductor channel and Bi₂SeO₅ as gate dielectric. The goal isn’t just to “shrink silicon further”; it’s to change lanes: 2D + GAA + 3D epitaxial to reduce electrical tension, better control the channel, and importantly, stack functionality without burning out the layer below.
Below are the essentials of this approach—why it matters and the remaining hurdles before it reaches the market.
Why Silicon Is Approaching Its Limit (and Simply Making It Smaller Isn’t Enough)
In a nanometric transistor, electrons no longer obey macro-scale physics. Quantum tunneling occurs through the dielectric; leakage currents increase even when “off”; and power per area rises to levels difficult to dissipate. Changing geometry—from planar to FinFET, then to GAAFET (where the gate surrounds the channel “on all sides”)—improved electrostatic control, contained leaks, and extended scaling margins. But the fundamental material, Si and SiO₂ or high-κ oxides deposited on top, still imposes limits: interface traps, dielectric constants forcing minimum thicknesses, and processing temperatures incompatible with stacking active layers.
The consequence: more complex, costly nodes, shorter gains, and a supply chain concentrated in few companies. It’s both a physical and geopolitical problem.
Peking’s Proposal: a Bi₂O₂Se GAAFET… and Its Own “Native” Dielectric
The team led by Hailin Peng (Peking University) constructs a two-dimensional GAAFET where:
- The channel is Bi₂O₂Se, a 2D semiconductor with high electron mobility and a laminar structure (layers bonded by van der Waals forces) that promotes clean interfaces and atomic-scale thickness control.
- The gate is isolated with Bi₂SeO₅, a dielectric that can grow from the channel itself (via controlled oxidation), fostering a crystalline, stable interface unlike heterogeneous pairings (if you’ve experienced traps with Si/ALD-HfO₂, this pairing hints at why it’s promising).
Why Does This Pair Matter?
- Electrostatic “envelope” control. As a GAA device, the gate surrounds the 2D channel, reducing subthreshold slope, increasing on/off ratios, and better managing variability in short channels. The study shows the 2D GAAFET has better control than a single-gate FET with the same channel.
- Refined interface. The Bi₂O₂Se/Bi₂SeO₅ duo exhibits low formation energy and atomic flatness in STEM images, essential for low dispersion and low hysteresis. Avoiding aggressive chemical “glues” reduces trap states at the channel-dielectric boundary.
- High-κ dielectric. The effective dielectric constant of Bi₂SeO₅ enables sub-nanometer EOT in configurations that avoid leakage, unlike SiO₂ (~3.9) which struggles to thin without leaks. This means more control at lower voltages.
- Low-temperature processing. Low T lamination/epitaxy prevents damaging the underlying layer, supporting monolithic 3D stacking without destroying previous layers.
True 3D Monolithic: From Flat to “Skyscraper” Transistors
The 3D monolithic integration (distinct from pack stacking) involves fabricating functional transistors and connecting them vertically in successive layers within the same wafer, without reheating or damaging the underlying tiers. This shortens the distance between logic and memory, reduces parasitic capacitances, and opens avenues for density scaling without relying on impossible lithography.
Architecturally, this aligns with monolithic 3D CMOS: stacked NMOS and PMOS (CFET), nearby logic macros with SRAM, buffers, and caches literally above the critical logic. Crucially, it operates at lower voltages, easing thermal management—less heat per mm² per layer—making total thermal loads more manageable.
Does This Work? Insights From the Paper (and What’s Missing)
The report highlights:
- 2D GAAFETs with a channel ≈2.4 nm and dielectric per side ~4.0 nm; gate lengths reduced to ~30 nm and functional arrays.
- Subthreshold slopes near thermionic limit and aligned with IRDS targets forecasted for the decade, with hysteresis contained in cyclic tests.
- Quantified contact resistances via Transfer Length Method (TLM), with variability characterized in short-channel devices.
- Thermodynamic stability of the Bi₂O₂Se/Bi₂SeO₅ interface, compared against traditional Si/SiO₂ and MoS₂/HfO₂ pairs, based on DFT calculations and structural evidence.
What’s not yet achieved is a complete “microprocessor” or a wafer-scale demo at 12″. We’re talking about transistors and arrays with promising device metrics—on/off, subthreshold swing, gm vs. Lch— and a thermal ceiling compatible with stacking. The step from “paper to factory” remains, but the material + process combo eases two major silicon bottlenecks: interface and integration temperature.
Three Clear Impacts If This Scales Up
- Chip architecture: With monolithic 3D and lower voltages, logic and memory can be co-localized to eliminate some memory-CPU/AI bottlenecks. Think of inference matrices with vertically stacked buffers, or SRAM with much lower latencies. Less distance = less energy per operation.
- Data centers: Every % of efficiency matters. As operation voltage drops and logic density increases without boosting parasitic losses, the PUE (and TCO) could improve in two ways: chip and room (less heat to evacuate per useful operation).
- Silicon Geopolitics: If 2D materials and their native dielectrics are industrialized, new value chains emerge outside the existing Si-centric ecosystem. This doesn’t “kill” silicon—industry transitions don’t happen overnight—but it creates a front where countries with export restrictions can innovate and leapfrog.
The “Drawbacks” Not to Be Ignored
- Industrial scaling: Moving from lab chips to high-volume manufacturing requires large wafers (8–12”), controlled variability, and competitive yield. None of which is trivial in 2D.
- Contacts and metallization: Creating contacts to 2D channels free of pinning and with low Rc at scale remains challenging, though progress (van der Waals contacts, selective metallization) is being made.
- EDA ecosystem and PDKs: Enabling standard cells, SRAMs, and 3D flows requires compact models and robust PDKs; scientific bases are there, but a real product for designers is still missing.
- Thermal compatibility in stacking multiple active layers. Even with low-T processing, the chip in use will dissipate heat; managing vertical thermal flow is a dedicated challenge.
Is Moore’s Law Dying?
Rather than “dying,” it’s transforming. Pure geometric scaling is giving way to new axes: 2D materials, GAA geometries, monolithic 3D stacking, co-design of logic and memory, heterogeneous packaging, and specialization based on workload (AI, accelerators, CFETs, chiplets). The work from Beijing suggests that the future “law” will be a combination of vertical density, low voltage, and clean interfaces rather than just nanometers as a marketing metric.
What To Watch From Now On
- Independent replication: External labs reproducing Bi₂O₂Se/Bi₂SeO₅ GAAFETs with comparable metrics.
- More complex 3D demonstrators: CMOS inverters, SRAM cells, and stacked logic blocks with low-R/C vertical interconnects.
- Silicon integration pathways:Hybrid approaches (e.g., 2D logic on silicon back-end) to accelerate adoption.
- Roadmaps: Large-scale wafer tools and deposition, lithography, metrology processes adapted for volume 2D fabrication.
Conclusion
Microelectronics isn’t lacking ideas: when silicon reaches physical limits, 2D materials and monolithic 3D integration provide alternative lanes. The pairing of Bi₂O₂Se and Bi₂SeO₅ shows that channel and dielectric can co-evolve to restore electrostatic control, lower voltages, and enable stacking. While industry engineering and scaling from paper to commercial SoC require time, the signals are clear: future Moore’s Law will be more about dimensions and interfaces than just nanometers as a marketing term.
FAQs
What is a 2D GAAFET and how does it differ from a silicon FinFET?
A GAAFET (Gate-All-Around) surrounds the channel with the gate on all sides, offering better electrostatic control than a FinFET, where the gate covers three sides of the channel. When the channel itself is 2D (atomic-thin, van der Waals interfaces), it reduces traps and dispersion at the interface, improving on/off ratios, subthreshold swing, and variability in short channels.
Why choose Bi₂O₂Se as a semiconductor and Bi₂SeO₅ as a dielectric?
Because they form a stable, planar interface at the atomic level: the dielectric can be grown from the channel itself (via controlled oxidation), reducing defects. Moreover, Bi₂SeO₅ is high-κ, allowing very low EOT without inducing leakage—something hard to achieve with SiO₂ (~3.9). Additionally, Bi₂O₂Se provides high mobility within laminar structures.
How does monolithic 3D integration improve over existing 3D packaging?
Existing 3D packaging (like chiplets, HBM) stacks pre-made chips; monolithic 3D fabricates active layers directly on top of each other within the same wafer, connected via dense vertical interconnections. This minimizes distances between logic and memory, greatly reducing latency and energy per access.
When will we see commercial processors utilizing these 2D materials?
In the short term, more realistic are demonstrators (inverters, SRAM, logic blocks) and hybrid integrations with silicon, rather than full CPUs/GPUs. Biggest challenges include wafer-scale manufacturing, process variability, contacts, and PDK development. Over the medium term, if wafer-scale and throughput milestones are met, we might see specialized 2D logic blocks coexisting with silicon.
What implications would this have for data centers and energy efficiency?
Lower operation voltages and monolithic stacking translate into less energy per operation and reduced data movement distances. In large-scale AI and analytics, these improvements lower the overall system footprint and thermal management, positively affecting PUE and TCO.
