Synopsys, Inc. (Nasdaq: SNPS) has announced an expanded collaboration with TSMC for the development of designs in advanced nodes, deployed in a variety of artificial intelligence, high-performance computing, and mobile applications. The latest collaboration includes a co-optimized IC photonic flow, which addresses the application of silicon photonics technology in the pursuit of improved energy efficiency, performance, and transistor density.
Synopsys has highlighted the industry’s confidence in its digital and analog design flows, production-ready for TSMC N3/N3P and N2 process technologies. Both companies are collaborating on next-generation AI-driven flows, including Synopsys DSO.ai™, for design productivity and optimization. Additionally, Synopsys is developing a broad portfolio of Foundation and Interface IP on TSMC N2/N2P. In a related announcement, Keysight, Synopsys, and Ansys have introduced a new integrated RF design migration flow from TSMC’s N16 process to its N6RF+ technology.
“Advancements in Synopsys’ production-ready EDA flows and the integration of photonics with our 3DIC Compiler, supporting the 3Dblox standard, combined with a broad IP portfolio, enable Synopsys and TSMC to help designers achieve the next level of innovation for their chip designs in TSMC’s advanced processes,” said Sanjay Bali, VP of Strategy and Product Management for the EDA Group at Synopsys. “The deep trust we have built over decades of collaboration with TSMC has provided the industry critical EDA and IP solutions that deliver quality results and productivity gains with faster node-to-node migration.”
“Our close collaboration with Open Innovation Platform (OIP)® ecosystem partners like Synopsys has enabled customers to address the most challenging design requirements, all on the cutting edge of innovation from angstrom-scale devices to complex multi-die systems in a variety of high-performance computing designs,” said Dan Kochpatcharin, Managing Director of Design Infrastructure Management Division at TSMC. “Together, TSMC and Synopsys will help engineering teams create the next generation of differentiated designs on TSMC’s most advanced process nodes with faster time to market.”
Synopsys’ production-ready digital and analog design flows for TSMC N3P and N2 process technologies have been deployed in a variety of AI, high-performance computing, and mobile designs. The AI-driven analog design migration flow allows for quick migration from one process node to another. A new flow is available for TSMC N5 to N3E migration, adding to Synopsys’ established flows for TSMC N4P to N3E and N3E to N2 processes.
Additionally, interoperable Process Design Kits (iPDKs) and Synopsys IC Validator™ physical verification runsets are available for design teams to efficiently transition to TSMC’s advanced process technologies. Synopsys IC Validator provides complete chip physical verification to handle the growing complexity of physical verification rules. Synopsys IC Validator is now certified on TSMC N2 and N3P process technologies.
The high data processing volume for AI training requires low-latency, energy-efficient, high-bandwidth interconnections, driving the adoption of optical transceivers and close/compound optical packaging using silicon photonics technology. Synopsys and TSMC are developing end-to-end flow solutions for multi-die electronic and photonic designs using TSMC’s Compact Universal Photonic Engine (COUPE) technology to enhance system performance and functionality. This flow covers photonic IC design with Synopsys OptoCompiler™ and integration with electric ICs using Synopsys 3DIC Compiler and Ansys multifysics analysis technologies.
Synopsys is developing a broad portfolio of Foundation and Interface IP for TSMC N2 and N2P process technologies to enable faster silicon success for complex AI, high-performance computing, and mobile SoCs. High-quality IP PHY on N2 and N2P, including UCIe, HBM4/3e, 3DIO, PCIe 7.x/6.x, MIPI C/D-PHY and M-PHY, USB, DDR5 MR-DIMM and LPDDR6/5x, allows designers to benefit from the PPA improvements of TSMC’s most advanced process nodes. Additionally, Synopsys provides a proven silicon Foundation and Interface IP portfolio for TSMC N3P, including Ethernet 224G, UCIe, MIPI C/D-PHY and M-PHY, USB/DisplayPort and eUSB2, LPDDR5x, DDR5, and PCIe 6.x, with DDR5 MR-DIMM in development. Synopsys’ IP for TSMC’s advanced processes has been adopted by dozens of leading companies to accelerate their development time.