The semiconductor industry has been accustomed for years to headlines about miniaturization, but the leap now proposed by the South Korean industry points to a frontier that, until recently, sounded more like laboratory research than a roadmap. The Korean Institute of Semiconductor Engineers has published its “Semiconductor Technology Roadmap 2026”, a document projecting the technological evolution over the next 15 years. It sets the year 2040 as the beginning of a new era: the arrival of logical circuits “0.2 nm” and the deployment of structures like CFET and 3D monolithic architectures.
The forecast, reported by ETNews, speaks of a drastic reduction in circuit sizes—down to one-tenth of current levels—and of transitioning from nanometer-scale to Angstrom-scale (A), a unit used when operating in ranges of tenths of nanometers.
From the current 2 nm to the great leap in 2040
The roadmap comes at a time when the industry is beginning to solidify the transition to more advanced transistor architectures. For example, Samsung has introduced its Exynos 2600, a mobile chip based on a GAA (Gate-All-Around) 2 nm process, marking a milestone that sets the bar for cutting-edge technology in 2025. From there, the Korean roadmap envisions a series of continuous improvements that should culminate, by 2040, in logic nodes of “0.2 nm,” supported by two key concepts:
- CFET (Complementary Field-Effect Transistor): an evolution of transistors seeking to stack and combine complementary devices to continue scaling density and performance.
- Monolithic 3D structuring: an approach aiming to go beyond traditional stacking (advanced packaging) by creating more tightly integrated functional layers.
Essentially, the core message is clear: if planar scaling approaches its limits, industry needs more verticality and new architectures to keep advancing.
The fine print of “0.2 nm”: more than a number, a symbol
The “0.2 nm” figure is powerful but also delicate. In reality, node names don’t always correspond to a single physical measurement (like gate length) and usually condense multiple improvements: density, efficiency, performance, new materials, and design rules. That’s why when a roadmap mentions “0.2 nm,” it often refers to a technology class or a scaling milestone, rather than all transistor elements literally measuring that figure.
Nevertheless, the document serves as a statement of intent: South Korea aims to formalize its industry’s aspiration to lead the next phase, even as scaling faces increasingly complex problems—variability, leaks, heat dissipation, interconnect limits, and manufacturing processes nearing physical limits where physics becomes the biggest adversary.
Nine “core” technologies: from process to AI chips and quantum computing
The roadmap isn’t just about shrinking nodes. According to ETNews, its goal is to strengthen technological and industrial competitiveness over the long term, energize academic research, and guide talent development strategies. To do this, it structures its projections around nine essential technologies:
- Semiconductor devices and processes
- Semiconductors for Artificial Intelligence
- Optical interconnection
- Wireless connection semiconductor sensors
- Cabled connection semiconductors
- PIM (Processing-In-Memory)
- Packaging
- Quantum computing
- (and the set of technological lines grouped as evolution axes in the document)
This list reveals a shift in mindset: the future depends not only on “nodes” but on the whole system. Speed isn’t just about smaller transistors anymore; it’s also about better interconnects, faster memory, advanced packaging, and architectures tailored for specific workloads—especially in Artificial Intelligence.
Memory: thinner DRAM, multi-layer HBM, and bandwidth jumps
The most striking predictions for the market concern memory, the major bottleneck of the AI era. ETNews reports foresee:
- DRAM: reducing circuit size from 11 nm to 6 nm
- HBM (High-Bandwidth Memory): increasing from 12 layers and 2 TB/s bandwidth to 30+ layers and 128 TB/s
This is an aggressive outlook but aligns with sector trends: AI accelerators and high-performance systems are increasingly limited by how much data they can move, rather than just raw computing power. In this context, the evolution of HBM—more layers and wider bandwidth—becomes a strategic race.
NAND: from 321 layers to 2,000 layers
The roadmap also quantifies a bold goal: NAND flash would grow from the current 321 layers to an estimated maximum of 2,000 layers.
The message is twofold: firstly, the industry continues to bet on vertical stacking as a growth path. Secondly, it acknowledges that increasing complexity—manufacturing, performance, costs—will be inevitable, and that storage will remain a central component for data centers and the device ecosystem.
AI chips: from today’s levels to “TOPS” at a different scale
Regarding AI semiconductors, ETNews offers another forecast encapsulating the roadmap’s logic: in 15 years, a significant performance leap measured in operations per second is expected.
The report compares the starting point—mentioned as 10 TOPS per watt—with a future where chips could reach 1,000 TOPS for training and 100 TOPS for inference.
Beyond the numbers, the message is clear: the growth of AI won’t be sustainable without radical improvements in efficiency and architecture, and South Korea’s industry aims to be at the forefront of this transformation.
An industrial policy as well as a technological roadmap
Such documents are not just predictions—they serve as coordination tools among industry, academia, and government. ETNews emphasizes that the Institute plans to update and revise the roadmap periodically, expanding its scope according to technological needs.
In a global landscape marked by competition among blocs—US, China, South Korea, Taiwan, and Europe—a roadmap like this functions both as an internal message (investment priorities, talent development) and an external statement (leadership ambitions). Most importantly, it confirms that the future of chips isn’t dictated by a single metric but by a combination of new transistor architectures, 3D integration, advanced memories, interconnects, and packaging.
Frequently Asked Questions
What does it mean that the industry is entering the “angstrom era” in semiconductors?
It involves working at scales of tenths of nanometers and tackling increasingly demanding physical limits. Essentially, it’s a way to describe a new phase of miniaturization and architecture, not just a change in units.
Is a “0.2 nm” chip literal or just a way of talking about technology nodes?
It’s generally a reference to a “class” of node and a set of technological improvements. Node names don’t always correspond to a specific physical dimension within the transistor.
What is CFET and why is it key for 2040?
CFET is a complementary transistor architecture intended to continue increasing density and efficiency as traditional scaling becomes insufficient. It’s often associated with strategies for more vertical integration.
Why do HBM and bandwidth matter so much in the AI era?
Because many AI systems are limited by data movement. Increasing layers and bandwidth in HBM helps feed the computation with more data and fewer bottlenecks.
via: ETNews