SK hynix is already working on technologies to push HBM (High Bandwidth Memory) past today’s configurations. At Hot Chips 2026, the company showed off hybrid bonding, new heat dissipation methods, more TSV connections, and future 3D designs that could place memory directly over AI accelerators. It also listed Intel’s EMIB among the 2.5D packaging options it’s considering for integrating HBM.
The future of HBM in 30 seconds
- SK hynix is exploring hybrid bonding to get past 16-layer stacks and shorten connection distances.
- HBM4 tops 2 TB/s per stack and doubles its I/O lines to 2,048 bits.
- The company is developing I-HBM to pull heat out of particularly hot spots.
- It’s also weighing Intel’s EMIB alongside several CoWoS variants for 2.5D packaging.
- Longer term, SK hynix is studying 3D integration with HBM placed directly over the accelerators.
The presentation helps explain why memory has become one of the trickiest parts of an AI accelerator. Boosting GPU performance is no longer just about adding compute units. You also have to feed them data fast, which means raising capacity, bandwidth, and connections all at once.
HBM has chased that goal by stacking DRAM chips vertically. The layers talk to each other through TSVs (Through-Silicon Vias), vertical connections that run through the silicon. The memory stack and the processor stay separate chips, usually sitting side by side on an interposer.
But that architecture is starting to hit physical limits that get harder to solve each generation.
HBM4 takes packaging to another level of complexity
SK hynix uses HBM3E to show how far this has come. Against a reference GDDR6 setup with 24 GB and 768 GB/s, four HBM3E stacks can reach up to 144 GB and around 4 TB/s in about half the space, per the company’s data.
HBM4 raises the bar again.
SK hynix’s latest generation has a 2,048-bit interface, up from the 1,024 bits used before, and can top 2 TB/s of bandwidth per stack. The documentation includes DRAM chips up to 24 Gb, with 12-layer configurations in production and 16-layer designs in qualification.
A stack can also carry more than 20,000 TSVs and 16,148 microbumps at the base, which shows how much performance now leans on advanced packaging.
More connections need more space.
Even as manufacturers shrink TSV size and spacing, adding more of them raises the area needed. A tougher problem for AI accelerators is heat.
SK hynix estimates that roughly doubling bandwidth every two generations could create about 2.2 times more thermal load on current process and packaging technologies.
That’s an especially delicate limit, since HBM stacks sit very close to GPUs that can draw hundreds of watts.
Hybrid bonding to get past 16 layers
One of SK hynix’s answers is hybrid bonding, which connects layers with far smaller joints than traditional microbumps.
HBM packaging currently uses two main methods: TC+NCF (Thermo-Compression + Non-Conductive Film) and MR-MUF (Mass Reflow Molded Underfill).
Each has trade-offs. TC+NCF resists chip deformation better but has higher thermal resistance and lower productivity. MR-MUF improves productivity and heat transfer but brings deformation and gaps between chips.
SK hynix uses an evolution of MR-MUF in its 16-layer HBM3E designs, but sees hybrid bonding as a technology it needs to keep raising stack height.
The company’s data suggests connections with pitches below 18 microns. Hybrid bonding would also allow roughly 24% thicker memory chips and, by its measurements, up to 35% lower thermal resistance even with more layers.
That matters because thinning chips to pack in more layers makes manufacturing and handling harder.
So the industry could move from today’s 12- and 16-layer configurations toward future stacks of 16 to 20 layers, though SK hynix didn’t give a commercial timeline for these designs in this presentation.
I-HBM aims to pull heat straight from hot spots
The Korean manufacturer is also developing I-HBM to tackle hot spots inside the memory stack itself.
The idea is to add a component with high thermal conductivity and electrical insulation into the PHY interface between chips, creating a dedicated path to vent heat away from the most concentrated areas.
SK hynix says this design can cut thermal resistance by more than 30%.
The concept fits other industry research into managing memory heat at the package level, rather than relying only on cooling placed over GPUs and memory modules.
The company is also weighing distributing TSVs dedicated to power delivery across different chip zones, to improve the PDN (Power Delivery Network) that feeds the various components.
The recurring challenge stays the same: higher bandwidth means more connections and more energy to keep it all running.
Intel’s EMIB considered alongside CoWoS
Another detail from the talk is the mention of EMIB (Embedded Multi-die Interconnect Bridge) from Intel as one of the technologies SK hynix is considering for 2.5D HBM.
EMIB uses small silicon bridges embedded in the substrate to connect neighboring chips, avoiding a large silicon interposer in certain setups.
It’s listed alongside CoWoS-S, CoWoS-R, and CoWoS-L, different variants of TSMC’s advanced packaging.
Including EMIB is technically relevant, but it doesn’t confirm a commercial deal between Intel and SK hynix for future HBM manufacturing. The data is about integration and packaging methods.
There’s also speculation about possible corporate moves between the two on memory, but the documentation doesn’t confirm any firm project.
The next step could be stacking memory directly on the accelerator
The most intriguing part of the presentation looks past current 2.5D packaging.
SK hynix envisions 3D architectures where HBM could sit directly over the accelerators.
HBM is already three-dimensional in that its DRAM chips stack vertically. Even so, the whole stack usually sits next to the GPU or XPU.
The next move would be to integrate memory and processor vertically, for a more direct connection.
Cutting the physical distance would allow shorter connections and could raise bandwidth while lowering the energy spent moving data.
That’s exactly where different semiconductor makers are starting to look, pushed by AI model growth. Bigger model weights and deeper cache hierarchies demand more capacity, and compute units need faster data access.
The catch is that putting memory on top of high-power processors makes heat harder to shed. It also raises questions about power delivery, manufacturing yield, defect repair, and packaging cost.
So treat SK hynix’s presentation as a forward-looking vision, not an immediate 3D HBM product announcement.
HBM4 and later generations will depend more and more on advances in packaging, vertical interconnects, power delivery, and especially cooling, not just on improving the DRAM itself. Those factors will decide how much further bandwidth can grow for AI accelerators.
Frequently Asked Questions
What bandwidth can SK hynix’s HBM4 reach?
SK hynix’s data indicates HBM4 can deliver over 2 TB/s per stack using a 2,048-bit interface. Actual performance depends on the specific configuration.
What is hybrid bonding in HBM for?
It creates smaller connections between memory layers and can improve thermal behavior. SK hynix sees it as one of the technologies for getting past current stacks of up to 16 layers.
What is I-HBM?
It’s a technology SK hynix is studying to create a dedicated heat-venting path near hot spots within the memory interface. The company reports it can cut thermal resistance by over 30%.
Will SK hynix use Intel’s EMIB?
SK hynix showed EMIB as one of the 2.5D packaging options it’s considering, alongside several CoWoS variants. The documentation doesn’t confirm a specific commercial product based only on EMIB.
Source: wccftech
