DRAM memory is approaching an uncomfortable technical frontier. For decades, manufacturers have managed to increase density and reduce cost per bit by shrinking cells, refining lithography, and improving materials. But in the 1D generation, associated with the seventh wave of 10 nm class DRAM and the shift toward geometries increasingly close to the physical limit, this approach is beginning to fall short.
Samsung Electronics and SK Hynix, the two major South Korean memory manufacturers, are pursuing different paths to overcome this bottleneck. Samsung is researching a vertically stacked DRAM with 16 layers, while SK Hynix is working on a 4F² Vertical Gate structure that pushes architecture closer to the traditional planar design before moving into fully three-dimensional DRAM. Both companies will present advancements at this year’s VLSI Symposium, one of the most important technical forums for processes, devices, and advanced memory.
Samsung Looks Upward with a 16-Layer DRAM
Samsung’s proposal is based on a simple but complex-to-manufacture idea: if horizontal space runs out, grow vertically. Their VS-DRAM technology, short for Vertically Stacked DRAM, involves stacking memory cells in 16 levels to increase density without relying solely on further reducing line widths.
The technical summary for the 2026 VLSI Symposium indicates that Samsung will demonstrate a 16-layer vertical DRAM with Gate-All-Around transistors and horizontally laid storage capacitors. The use of GAA structures is notable because, until now, this configuration—where the gate surrounds the transistor channel—has been primarily associated with cutting-edge logic processes below 3 nm. In logic applications, GAA allows better control of current and reduces leaks. In DRAM, the challenge is greater since each cell combines a transistor and a capacitor.
This is the core of the problem. Conventional DRAM cells store information as electrical charge in a capacitor and use a transistor to access it. As cells shrink, maintaining sufficient charge, controlling leaks, and avoiding interference between neighboring elements become increasingly difficult. The capacitor must still reliably retain information, but available space diminishes generation after generation.
Samsung aims to solve this by flipping the capacitor from its traditional vertical growth pattern—making it more difficult to manufacture—and placing it horizontally within a stacked architecture. Additionally, they are exploring a Peri-on-Cell approach, where peripheral circuitry is fabricated on a separate wafer and then bonded to the wafer containing the memory cells. This resembles efforts seen in NAND memory, where moving logic beneath or alongside the memory array has improved area efficiency.
This approach suggests a DRAM architecture closer to 3D logic memories but still faces the challenge of bringing such complexity into production with acceptable performance, reliability, and costs. Stacking cells is ineffective if the manufacturing process severely reduces yield or introduces electrical variability that is hard to control.
SK Hynix Pursues the 4F² Design
SK Hynix is exploring a different route. Its immediate focus is on a 4F² Vertical Gate DRAM structure, where “F” represents the minimum feature size of the process. Moving from typical 6F² designs to 4F² allows for a reduction in cell area and potentially increases chip density. Industry estimates suggest this reduction could be around 30%, though the final outcome depends on the specific process and design.
At the VLSI Symposium, SK Hynix will present the electrical characteristics of its 4F² Vertical Gate DRAM, which incorporates Bit-Line Shielding and Back Gate. The Bit-Line Shield aims to reduce coupling noise between bit lines—a problem exacerbated when cells are placed closer together. The Shared Back-Gate improves transistor threshold control and helps stabilize read/write operations.
SK Hynix is also investigating die thinning techniques to ensure stable operation of circuits within wafer-bonded configurations. This detail is critical because, if next-generation DRAM relies on integrating memory arrays and peripheral circuits via bonding techniques, controlling die thickness, alignment, mechanical stresses, and thermal dissipation becomes vital variables.
The manufacturer previously outlined a long-term roadmap in 2025, where the 4F² VG platform was seen as a step toward more integrated DRAM solutions with lower power consumption and higher speed. The key difference with Samsung lies in the degree of disruption; SK Hynix appears to prefer a more gradual transition—reducing cell size and improving electrical control before adopting more aggressive 3D structures.
Why These Changes Matter for AI and HBM
The battle for DRAM is not purely academic. Memory demand is booming due to AI servers, accelerators, HBM, high-performance CPUs, and increasingly demanding mobile devices. HBM, which stacks multiple DRAM chips and connects them with high bandwidth, has become one of the most valuable components in AI systems. However, its advancement also depends on the evolution of underlying DRAM cells.
If conventional DRAM cannot continue scaling efficiently and densely, increasing capacity becomes more costly and difficult. This impacts DDR, LPDDR, GDDR, and HBM modules, each with different priorities. In AI servers, where memory capacity, bandwidth, power consumption, and space are critical, any real improvement in density or efficiency can lead to substantial industrial benefits.
The 1c generation has been viewed as the culmination of conventional structuring according to many industry analyses. Starting from 1d and subsequent nodes, shrinking line dimensions is no longer sufficient. Manufacturers need to change cell geometry, move circuitry, introduce bonding techniques, improve materials, and better control leaks and interference. That’s why Samsung and SK Hynix are presenting proposals at technical forums that, just a few years ago, would have seemed more like research lab ideas than near-term roadmaps.
The winner will not necessarily be the one who first demonstrates the most impressive structure, but the one capable of producing it at volume with good performance, reasonable costs, and compatibility with customer needs. In memory, a brilliant idea can take years to commercialize profitably. The industry is full of promising technologies that have failed to overcome economic barriers for mass production.
The difference now is market pressure. Artificial Intelligence is consuming HBM capacity; data centers require more memory per server; manufacturers seek every advantage to improve margins and supply. If Samsung can demonstrate that 16-layer vertical DRAM is scalable, it could open a more radical pathway. Conversely, if SK Hynix successfully brings the 4F² VG design into stable production, it may enable a more controlled, cost-effective transition.
The next-generation DRAM will be decided not just by nanometer nodes but by architectural approaches, vertical integration, wafer bonding techniques, leak control, and the ability to produce millions of chips with minimal variations. Memory, which advanced largely unnoticed for many years, is once again central to cutting-edge computing.
Frequently Asked Questions
What is 1D DRAM?
1D DRAM is an advanced generation within the 10 nm class. It marks a stage where traditional cell scaling begins to require deeper structural changes.
What is Samsung proposing with VS-DRAM?
Samsung is researching a vertically stacked DRAM with 16 layers, using Gate-All-Around transistors and horizontal capacitors, to increase density without relying solely on planar size reduction.
What is SK Hynix’s 4F² Vertical Gate DRAM?
It is an architecture that reduces cell area through vertical gate structures, combined with Bit-Line Shielding and Back Gate techniques for improved electrical stability.
Why are these developments important for AI?
AI systems demand more memory, higher bandwidth, and better energy efficiency. If DRAM cannot scale effectively, products like HBM and high-performance servers become more expensive and complex.