The Japanese Rapidus has taken a significant step in the global race for advanced semiconductors. The company has revealed, for the first time, logical density figures for its 2-nanometer “2HP” process, positioning it at the same level as TSMC’s N2 and far ahead of Intel 18A.
This progress, still in its early stages, places Rapidus in an unexpected but ambitious position, capable of breaking into a territory traditionally dominated by industry giants like TSMC, Samsung, and Intel.
Logical density: the metric that makes the difference
According to information published by analyst @Kurnalsalts, the 2HP node from Rapidus reaches 237.31 million transistors per square millimeter (MTr/mm²). This is nearly tied with TSMC’s N2 (236.17 MTr/mm²), which has been considered the benchmark for next-generation nodes.
In contrast, Intel 18A falls behind with an estimated density of 184.21 MTr/mm², a significant difference despite its slightly smaller nominal node size. Analysts explain that the reason lies in the methodology: Intel prioritizes performance per watt and employs techniques like BSPDN (Backside Power Delivery Network), which consumes part of the front-side metal layers, reducing the raw density measurements in high-density (HD) libraries.
A bet on HD libraries and compact cells
Both TSMC and Rapidus have opted for HD (High Density) libraries, featuring a cell height of 138 units and a pitch of 45 nanometers (G45). This approach aims to maximize logical density and transistor count, suggesting both nodes will offer comparable capacity once in mass production.
The key will be how each manufacturer balances this density with parameters such as power consumption, performance per watt, and the ability to scale production without compromising performance.
TSMC and the advantage of scheduling
TSMC has already confirmed it will begin mass production of its N2 node in Q4 2025, solidifying its leadership in the roadmap.
Meanwhile, Rapidus aims to provide its process design kit (PDK) to customers in the first quarter of 2026, indicating it is still a step behind in terms of timeline. However, the logical density parity gives it a competitive edge that could attract strategic partners.
Japan seeks to regain prominence in semiconductors
Rapidus has emerged as Japan’s main bet to re-enter a significant role in the cutting-edge semiconductor market. The project benefits from government backing and international partnerships, and has attracted interest from players like NVIDIA, which are exploring alternatives to their heavy reliance on TSMC.
An innovative aspect is the adoption of a single-wafer front-end process, allowing adjustments in volume production before scaling. This technique aims to progressively improve performance and mitigate risks during early adoption phases.
The shadow of Intel and market fragmentation
Meanwhile, Intel is continuing its strategy with 18A, focusing on metrics like energy efficiency over raw density. This approach serves a different goal: to provide competitive advantages to its own foundry business and key clients, rather than leading in transistor density per millimeter square.
The comparison between Rapidus, TSMC, and Intel highlights how each player interprets “leading” in semiconductors differently:
- TSMC: Speed of execution and leadership in mass production.
- Rapidus: Competitive density combined with process innovation.
- Intel: Performance per watt and differentiation through technologies like BSPDN.
A wild card in the 2 nm race
The emergence of Rapidus as a direct competitor in the 2 nm node could reshape the global dynamics. Although it still needs to demonstrate large-scale manufacturing capacity and yield reliability, its progress indicates Japan is committed to not staying out of the race.
The lingering question is whether the market, dominated by strategic alliances and highly concentrated supply chains, will accommodate a new player capable of balancing power between Asia, the U.S., and Europe.
Frequently Asked Questions (FAQ)
1. What does logical density in semiconductors mean?
It measures how many transistors can fit into a square millimeter of silicon. The higher the number, the more computing power in less space.
2. Can Rapidus truly compete with TSMC?
In logical density, yes. However, TSMC maintains advantages in experience, production volume, and ecosystem maturity.
3. Why does Intel lag behind in density with 18A?
Its node uses technologies focused on efficiency and performance per watt, which reduces the density in conventional metrics.
4. When will 2 nm nodes be available?
TSMC plans to start mass production in Q4 2025, while Rapidus will offer its PDK early in 2026, with scaled production following thereafter.