Rapidus accelerates towards 2 nm: Japan aims to compete in the “post-TSMC” league

The global race for cutting-edge semiconductors has a new player eager to beat the clock: Rapidus. The Japanese foundry, backed by the country’s industrial ambitions, is preparing for a leap that just a few years ago seemed unlikely: bringing 2 nm class chips into production in the second half of FY2027, with an aggressive initial ramp-up and a nearly obsessive focus on performance (yield). In such advanced nodes, yield is the real line between an announcement and a sustainable business.

The roadmap being outlined for its Chitose (Hokkaido) plant positions Rapidus at the center of Japan’s semiconductor “rebirth”: not just as a technological project, but as a strategic move to reduce external dependence in a world of geopolitical tensions and increasing demand for chips for AI, automotive, and critical systems.

An ambitious ramp-up plan… with a silent enemy: yield

According to reports from Japan, the volume production plan begins with an initial monthly output of around 6,000 wafers, aiming to scale up to approximately 25,000 wafers per month during the first year of large-scale operation. This capacity jump, on paper, quadruples the production rate; practically, it focuses where it hurts most: improving yield while integrating and stabilizing hundreds of process steps, metrology, and inspection.

In advanced manufacturing, yield isn’t a detail: it’s the difference between a chip costing “X” or “3X.” And Rapidus understands this well. That’s why much of the industry discussion revolves around deploying a large number of tools simultaneously (more than 200 units in the ramp-up) and employing advanced process control to prevent scaling from becoming a permanent bottleneck.

From “prototype” to factory: the 2 nm milestone in Chitose

Rapidus has spent months trying to prove something crucial: that its line isn’t just a strategic investment, but a capable manufacturing site. Specialized media have reported that the company began producing test structures of 2 nm GAA transistors at its facilities—an important step toward validating tools and process flow maturity for the 2027 goal.

This approach has an interesting nuance: Rapidus is betting on a “single-wafer” process model (treating wafers individually) at the front-end. The goal is to improve fine control, speed adjustments, detect anomalies early, and gather more useful data for optimization, even using advanced analysis techniques. The cost is clear—greater complexity and potentially lower throughput—but the bet is straightforward: in 2 nm, process stability is worth its weight in gold.

Additionally, the company plans to provide the ecosystem with a critical tool: a Process Design Kit (PDK) to enable designers to prototype, explore rules, and prepare future tape-outs.

No orders, no factory: commercial pressure is already mounting

However, technological ambition alone doesn’t power the cleanroom’s lights. Rapidus needs contracts. That’s where the second major front emerges: securing top-tier clients to sustain the plant’s utilization once production begins at significant volumes.

In 2025, Reuters reported that Rapidus was in talks with major tech firms (including Apple and Google, among others) with plans to produce advanced chips in 2027. This is set against a backdrop where some market segments seek alternative supply chain options.

The same context includes a political-industrial component: Japan has committed funds and narrative to this effort. According to reports, the government planned to invest 200 billion yen during that fiscal year to support the goal of commercial production by 2027.

Automation and backend: the other battleground

If front-end lithography and manufacturing are the heart, the back-end (dicing, assembly, packaging) is becoming the arena where efficiency is gained—or competitiveness lost. In Japan, discussions have centered on Rapidus adopting a strategy of advanced automation in back-end, including technologies like chiplets, which enable integrating different blocks (CPU, memory, accelerators, I/O) into a single system-on-surface.

This aligns with a global trend: industry competes not just on nodes but on packaging, entire supply chains, and the ability to industrialize without escalating costs or timelines.

Fundamental insights: sovereignty, AI, and a very short window of opportunity

Rapidus seeks to capitalize on a rare window: a world demanding more advanced capacity but hesitant to rely solely on one industrial axis. Yet, the margin for error is minimal. The plan requires all three of these to happen simultaneously:

  1. Technology: the process must mature, and yield must reach commercially viable levels.
  2. Scale: the ramp-up must not be hampered by tool integration, maintenance, or variability issues.
  3. Demand: clients with enough volume must come to sustain the factory.

If any of these elements falters, the project risks remaining a “technological milestone” without translating into business. If they align, Japan could re-enter the forefront of advanced manufacturing with a home-grown player—not just as a material, equipment, and component powerhouse.


Frequently Asked Questions

What does “2 nm” mean, and why is it so important?
It’s a commercial label associated with a more advanced generation of manufacturing technology. In practical terms, it generally translates into improvements in energy efficiency and performance, which are critical for AI, mobile devices, servers, and embedded systems.

Why is yield the biggest risk at advanced nodes?
Because it determines how many good chips come off each wafer. Low yield means higher cost per chip and makes scaling production with sustainable margins challenging.

What is a PDK, and how can it attract clients before volume production?
The PDK is a package of rules, models, and libraries that enables chip design for a specific process. Having it early helps clients and partners prototype and plan products in advance.

Why is there so much talk about chiplets and advanced packaging?
Because a significant part of the performance boost now depends not just on the node but also on how different blocks (CPU, memory, accelerators, I/O) are integrated into a single package, improving flexibility and costs.

Sources: digitimes and wccftech

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