The LPDDR memory has been associated for years with smartphones, tablets, and ultra-thin laptops—devices where power consumption is as crucial as performance. However, that boundary is starting to shift. JEDEC, the organization that defines many key industry standards in semiconductors, has now advanced the next evolution of LPDDR6 and, with it, clearly indicates that this family of memory no longer wants to stay confined to the mobile market. The goal is to also target specific workloads in data centers, accelerated computing, and even Processing-in-Memory for inference applications.
The announcement is not an immediate commercial launch of new modules, but a preview of the roadmap JEDEC intends to include in the upcoming revision of the JESD209-6 LPDDR6 standard, whose original base was published in July 2025. Since then, the JC-42.6 subcommittee has been working to extend LPDDR6 beyond mobile platforms and bring it into scenarios where energy efficiency and memory density are becoming as important as pure bandwidth.
From Mobile Memory to a Potential Component for AI Servers
The shift in focus is no coincidence. AI systems are dramatically increasing pressure on memory: it’s not just about bandwidth, but also about higher capacity per channel, greater density per package, and reasonable power consumption. This is where LPDDR6 can gain ground over more traditional solutions in certain designs, especially in compact and highly integrated platforms. JEDEC explicitly states that the next version of the standard will serve selected data center and accelerated computing workloads, a cautious framing but very revealing of the market’s direction.
The industry is already preparing for this leap. SK hynix announced in March its first LPDDR6 module with over 10.7 Gbps, making it 33% faster and 20% more energy-efficient than LPDDR5X. Meanwhile, Samsung had already showcased its early LPDDR6 products at CES 2026. The message is clear: while the standard is still expanding, leading manufacturers are positioning for the next wave of products.
Additionally, LPDDR6 is not entering an empty field. This type of memory had already begun gaining prominence in AI systems with modular formats like SOCAMM and SOCAMM2, used in very specific NVIDIA platforms. Recently, Tom’s Hardware recalled that the Grace Blackwell Ultra GB300 uses SOCAMM and that the upcoming Vera Rubin system relies on SOCAMM2, which helps explain why JEDEC now aims to formalize a standard route for LPDDR6 SOCAMM2.
Key Features of the New LPDDR6 Roadmap
JEDEC has outlined four major improvements planned for the next revision of the standard. The first is a narrower bus per die, with a new x6 mode, in addition to x12 configurations and a transition from traditional binary widths to an x24 interface. Translated: increased flexibility to include more dies per package and boost capacity per component and channel—something JEDEC considers critical for AI-scale memory needs.
The second innovation is a flexible metadata carve-out, allowing customers to determine how much space to allocate to metadata versus usable capacity, based on reliability requirements. This change leans more toward data centers than consumer devices and underscores how JEDEC aims to adapt LPDDR6 to environments where data integrity and throughput efficiency can no longer be treated as simple extras.
The third and most headline-grabbing improvement is densities up to 512 GB. JEDEC does not claim this capacity is currently available but states that LPDDR6 opens the door to surpassing the current maximums of LPDDR5/5X to meet increasing demands for training and inference. This represents a technical direction rather than a finalized product specification for 2026.
The fourth element involves developing an LPDDR6 SOCAMM2 standard, designed to keep modules compact and replaceable, providing a pathway to upgrade from the current LPDDR5X SOCAMM2 modules. Here, industry efforts aim to solve an increasingly evident tension: enabling more memory in AI systems without always resorting to traditional server formats that consume more power and space.
JEDEC’s Forward-Looking LPDDR6 Roadmap
| Roadmap Element | Objective | Status |
|---|---|---|
| Narrower die interface (x6/x12/x24) | More dies per package and higher capacity per channel | Planned for next revision |
| Flexible metadata carve-out | Ajusts usable capacity based on reliability needs | Planned for next revision |
| Up to 512 GB densities | Scaling capacity for AI and acceleration | On the horizon |
| LPDDR6 SOCAMM2 | Miniaturize and standardize modules | In development |
| LPDDR6 PIM | Reduce data movement and improve inference | Close to completion |
Source: JEDEC, press release dated April 22, 2026.
Processing-in-Memory: The Other Major Front
The most ambitious part of the announcement involves LPDDR6 PIM. JEDEC affirms it is close to completing a standard for Processing-in-Memory based on LPDDR6—a technology integrating processing capabilities directly within memory to reduce data movement between memory and computation. Given that much of AI’s energy cost is linked to data transfer rather than computation, this approach makes a lot of sense for edge inference and certain data center scenarios.
The promise of PIM is not new, but it gains relevance as industry faces tighter physical and energy constraints. JEDEC claims that LPDDR6 PIM can deliver more inference performance and lower power consumption without sacrificing LPDDR’s traditional advantages—namely, efficiency designed from the ground up. If standardized successfully, it could become a vital component for systems where every watt counts.
A Standard Already Designed with AI in Mind
It’s important to recall that LPDDR6 did not start from zero. When JEDEC published JESD209-6 in July 2025, it introduced the standard as an evolution aimed at improving performance and efficiency in mobile and AI applications. It featured a dual subchannel architecture, support for 10.667 to 14.400 MT/s, enhanced concurrency, and features tailored for low power and high reliability. The key difference now is that the message extends beyond “AI devices” to include servers, SOCAMM2, and PIM applications with natural ease.
This does not imply that LPDDR6 will replace all data center memory. That is not the plan. But it signals a clear trend: AI is dissolving boundaries that once seemed quite stable. Mobile memory is no longer just mobile memory. And JEDEC has made it clear that it aims to make LPDDR6 much more strategic than LPDDR5X was just a year ago.
Frequently Asked Questions
What exactly has JEDEC announced about LPDDR6?
JEDEC has previewed new features for the upcoming revision of LPDDR6, including a narrower die interface, flexible metadata allocation, densities up to 512 GB, a LPDDR6 SOCAMM2 standard, and a LPDDR6 PIM standard.
Is LPDDR6 just for mobile devices anymore?
That’s the core shift. JEDEC states that the next evolution of LPDDR6 aims to extend this memory type to certain data center and accelerated computing workloads, in addition to mobile markets.
What is LPDDR6 PIM, and why does it matter?
It’s a form of Processing-in-Memory based on LPDDR6. It integrates computational capacity within the memory itself to reduce data movement, improve inference, and reduce power consumption.
Are LPDDR6 chips already on the market?
Yes. SK hynix and Samsung have already shown their first LPDDR6 products, with initial speeds around 10.7 Gbps. However, JEDEC’s roadmap indicates a much broader evolution in the coming years.