Over the past three years, the field of artificial intelligence has been defined by one word: GPU. NVIDIA became the most influential company in the sector because its accelerators were the fastest and most readily available way to train and run increasingly large models. However, the market is beginning to pay closer attention to another family of chips: ASICs, custom-designed processors tailored for specific workloads.
Johnny Shen, CEO of Alchip Technologies, believes that ASICs will still take time to surpass GPUs in overall market share, but they could grow at a faster pace in the coming years. This aligns with a clear trend among major cloud providers: reducing reliance on standard chips and developing their own silicon, more closely aligned with their needs in cost, power consumption, performance, and integration.
It’s not that GPUs will disappear. They remain the core component of much model training, AI development, and many mixed workloads. But the next phase of the market might not be dominated solely by the most flexible chip, but by the most efficient one for a particular task. ASICs have a natural advantage here.
Why hyperscalers want custom chips
GPUs have gained popularity because of their versatility. They are used for training, inference, research, simulation, graphics, data science, and many parallel workloads. This flexibility was perfect during an era when AI was evolving rapidly and no one wanted to commit to a too-closed architecture.
But when a workload stabilizes and is deployed at scale, the dynamics change. A hyperscaler that handles millions of inference requests, trains proprietary models, or designs AI services for internal products doesn’t always need maximum flexibility. It requires efficiency, cost control, supply assurance, and performance per watt. An ASIC can be precisely designed for that purpose.
Google has used TPUs for years. Amazon has promoted Trainium and Inferentia. Microsoft develops its own silicon and partners with third parties. Meta has created its own accelerators called MTIA. Broadcom has become a key partner for custom chips for large clients. In this landscape, Alchip occupies a different position: not competing as a GPU brand, but as a design and manufacturing services provider for companies looking to bring their own ASICs to advanced nodes.
According to TrendForce, during its latest financial report, Alchip stated that the design of a major customer’s chip went into mass production in May and is expected to drive revenue growth this year and next. The same sources suggest that a 3nm AI accelerator for a North American client will start ramping in shipments from Q3, while projects in 2nm are progressing with a tape-out target by year-end.
| Technology | Main Advantage | Limitation |
|---|---|---|
| GPU | Flexibility, mature ecosystem, broad software support | High cost, elevated power consumption, reliance on dominant suppliers |
| ASIC | Efficiency per watt, optimized cost, tailored design | Less flexible and more expensive to design initially |
| TPU / custom cloud accelerators | Vertical integration within large platforms | Typically tied to a specific provider |
| Chiplets + 2.5D/3DIC | Greater scalability, better mix of nodes, advanced packaging | Increased design, testing, and production complexity |
Economic pressures are significant. Alchip claims, citing industry sources, that ASICs can offer a total cost of ownership advantage of between 40% and 65% over commercial silicon alternatives in large deployments over several years. It also estimates that the AI ASIC market could grow from around $13 billion in 2024 to over $150 billion in 2030, with an average annual growth rate near 50%. These figures are ambitious and should be viewed as stakeholder estimates, but they reflect the market appetite.
AI is now designed at the system scale
The shift is not only economic but also technical. New AI accelerators can no longer be understood as isolated chips. Performance improvements depend on how compute dies, HBM memory, interconnects, chiplets, power delivery, advanced packaging, and cooling are combined.
Alchip emphasizes this concept with its 3DIC platform. The company states that AI processor design is moving toward a system-level approach: simply adding more transistors on the same die is no longer sufficient. Key questions include which parts are fabricated on advanced nodes, which blocks can be mounted on mature nodes, how chiplets connect, how they are powered, and how heat is dissipated.
Its 3.5D platform enables splitting large SoCs into optimized chiplets across different processes. Compute dies can be manufactured on advanced nodes, while I/O and memory functions stay on more economical nodes. The company claims this architecture combines horizontal scalability of chiplets with vertical stacking and advanced packaging technologies like CoWoS-S, CoWoS-R, CoWoS-L, and TSMC-SoIC-X.
The goal is to lower the limits of monolithic chips. As designs grow, issues like reticle size limitations, reduced manufacturing yields, more expensive masks, increased power consumption, and data movement challenges emerge. Advanced packaging allows the construction of larger systems without relying on a single massive die.
Alchip asserts that its platform provides up to 3 to 5 times the interconnect density, with 30–40% less energy per bit and latency up to 35% lower. These metrics, shared by the company, are not universal comparisons but highlight a key point: in AI, moving data becomes as important as computing it.
The battle shifts to TSMC and advanced packaging
The potential rise of ASICs does not eliminate bottlenecks; it shifts them. If more hyperscalers develop their own chips in 3nm, 2nm, and advanced packaging, the pressure on TSMC, CoWoS, substrates, OSAT, HBM, and test capacity will grow even more.
Johnny Shen pointed out that 3nm capacity is extremely tight and, from his perspective, this could be even more concerning than memory shortages. For a company like Alchip, maintaining a close relationship with TSMC isn’t merely operational—it is central to their business. Having the design ready is not enough; wafer allocation, packaging capacity, and a reliable supply chain for volume production are critical.
Alchip is actively working to strengthen this position. In March, it announced progress on its 2nm design platform, with ongoing projects, several tape-outs, and first-silicon successful test chips. It also mentioned that its platform allows combining 2nm compute dies with 3nm or 5nm I/O chiplets, a more practical approach until fully available 2nm I/O chiplets emerge.
This approach anticipates the future of AI accelerators: chips will be less “single pieces” and more assembled sets of specialized blocks within complex packages. The value will lie not only in logic design but also in physical coordination, packaging, supply chain, manufacturing, validation, and thermal performance.
| Critical factor | Why it matters in AI ASICs |
|---|---|
| Advanced node | Improves density and efficiency of compute dies |
| Chiplets | Enable mixing nodes and reduce risk of huge chips |
| HBM | Provides bandwidth for training and inference |
| CoWoS / 3DIC | Integrates memory, compute, and interconnects in an advanced package |
| Volume production | Determines if the design reaches the market on time and at a good cost |
| Software ecosystem | Can limit adoption if the ecosystem isn’t mature |
Production management becomes a strategic focus. Alchip highlights that, in high-volume ASICs, controlling WIP, inventory, performance metrics, cycle times, logistics, and capacity allocation is as vital as the design itself. A delay of months in an AI ASIC can disrupt a cloud roadmap, increase platform costs, or keep a customer dependent on more expensive GPUs longer.
A more fragmented market, not necessarily less dominated
The growth of ASICs doesn’t mean NVIDIA will lose its position overnight. Its advantages in software, CUDA, libraries, complete systems, AI networks, and customer relationships remain substantial. Also, GPUs continue to be more suitable for research, dynamic workloads, and deployments where flexibility matters more than extreme efficiency.
What could change is the composition of growth. If frontier model training remains concentrated on GPUs, but large-scale inference shifts partially toward ASICs, the market will become more fragmented. Expect more proprietary chips, semi-custom designs, and more partnerships among hyperscalers, ASIC designers, foundries, and packaging providers.
Another Taiwanese firm, GUC, has argued similarly: as AI moves from training to deployment, ASICs can deliver much higher performance per watt in inference compared to high-cost general-purpose GPUs. MediaTek has also raised its AI ASIC revenue forecasts, doubling its contribution estimate for this year from $1 billion to $2 billion, according to TrendForce.
This development carries important industrial implications. AI started as a race for models and GPUs; now it’s evolving into a full supply chain: design, IP, packaging, memory, manufacturing, software, data centers, and power. Alchip aims to occupy a strategic position in this middle ground, serving large clients who want proprietary chips but don’t necessarily build all design and manufacturing capacity alone.
The AI market isn’t transitioning from GPUs to ASICs with a simple switch. Most likely, it will be a long coexistence. GPUs will continue leading many workloads, while ASICs will make inroads where volume justifies custom design. For hyperscalers, this mix could be a way to regain control over costs. For providers like Alchip, it’s an opportunity to become an increasingly visible part of AI’s invisible infrastructure.
Frequently Asked Questions
What is an AI ASIC?
A custom chip designed to perform specific AI workloads, such as training or inference, with greater efficiency for that particular application than a general-purpose processor.
Will ASICs replace GPUs?
Not immediately. It’s more likely they will coexist. GPUs will continue to be vital for their flexibility and ecosystem, while ASICs will gain ground in highly repetitive, large-scale workloads.
Why are hyperscalers investing in ASICs?
Because they can reduce dependency on external suppliers, improve performance per watt, control costs, and tailor silicon to their own models and data centers.
What role does Alchip play in this market?
Alchip provides design services, advanced packaging, and manufacturing management for companies developing complex AI, HPC, and data center ASICs.