Ampere Quietly Launches New AmpereOne M: Up to 192 Arm Cores and 12 DDR5 Channels

Ampere Computing strengthens its commitment to cloud data centers with a new generation of high-performance processors with large memory capacity, as it transitions under the umbrella of SoftBank.

A discreet announcement for a significant technical leap

Without a press release, no official presentation, and only a mention on its X (Twitter) profile, Ampere Computing has launched the new AmpereOne M processors, an evolution of its AmpereOne architecture based on single-threaded custom Armv8.6+ cores. This quiet launch comes shortly after the company was acquired by SoftBank, which may explain the low profile with which they have introduced these powerful chips.

Up to 192 cores and 12 DDR5 memory channels

The new AmpereOne M processors offer configurations ranging from 96 to 192 cores without SMT (i.e., one thread per core), operating at frequencies of up to 3.6 GHz and with a TDP of up to 348 watts. The highlight is its new memory subsystem, which incorporates 12 DDR5-5600 channels, allowing for up to 3 TB of memory capacity per socket, although limited to one DIMM per channel.

This positions them particularly well for cloud workloads and Artificial Intelligence scenarios that require high bandwidth and a large amount of RAM.

Models presented:

Compatibility, cache, and connectivity

The new chips use a 7,228-pin FCLGA socket, which implies new motherboards. They are manufactured with the TSMC N5 (5 nm) process, the same as their predecessors, and each processor includes:

• 64 MB of system-level cache
• 2 MB of L2 cache per core
• Compatibility with 96 PCIe 5.0 lanes with bifurcation up to x4
• Full ECC support (SECDED and Symbol ECC)

All of this makes them ideal for modern server architectures where multiple accelerators, NVMe SSDs, network cards, and other high-performance peripherals are needed.

Comparison with competitors: AMD EPYC and Xeon Granite Rapids

Despite the increase in memory channels, the AmpereOne M faces formidable competition:

AMD EPYC 9965 (Turin family)

• 192 cores with SMT (384 threads)
• TSMC N5 process
• 12 DDR5-6000/6400 channels
• 128 PCIe 5.0 lanes
• TDP: 500 W
• AVX-512 support and mature x86_64 ecosystem

Intel Xeon 6 Granite Rapids / Sierra Forest

Although Intel has not yet released its equivalent models with 192 cores, the Xeon 6 lineup already offers variants focused on energy efficiency (Sierra Forest) and high performance for AI and HPC (Granite Rapids), with compatibility for DDR5 memory and support for CXL and PCIe 5.0/6.0 within the enterprise x86 ecosystem.

Looking ahead: AmpereOne MX on the horizon

According to the Ampere roadmap released in 2024, the next evolution will be the AmpereOne MX, featuring up to 256 cores, 12 DDR5 memory channels, and manufactured with the TSMC N3 (3 nm) node. This chip is expected to arrive in 2026, although current delays could push its launch into the second half of that year, coinciding with the future EPYC Venice from AMD and Xeon 7 Clearwater Forest from Intel.

Evaluation: A worthy competitor in the data center market?

Although AmpereOne M offers an attractive design with a high core density and ARM efficiency, the software ecosystem and vendor support remain challenges against AMD’s and Intel’s dominant x86. Additionally, the lack of SMT limits its parallel processing capability compared to the EPYC 9965, which doubles the threads per socket.

Nonetheless, its focus on energy efficiency, high-capacity memory, and backing from SoftBank could make it a viable alternative for cloud hyperscalers and specific AI deployments, especially in cost-effective models or ARM-native architectures.

For more information, visit Ampere.