The company will be the first to use TSMC’s 2 nm node in its EPYC Venice processors, but it is keeping negotiations open with other manufacturers like Samsung Foundry.
AMD has officially confirmed that it will be the first customer to use TSMC’s 2 nanometer (2 nm) node, doing so with its upcoming EPYC Venice processors, set to launch in 2026. In recent statements, the company has described this technology as the most advanced on the market, surpassing current offerings from Intel and Samsung. However, AMD has also indicated that it remains open to working with other fabs, including Samsung, if it enables better service for its customers.
The leap to 2 nm represents a key milestone in AMD’s technological roadmap, firmly committing to energy efficiency and performance per watt. Lisa Su, the company’s CEO, recently visited TSMC’s facilities in Arizona to formalize this agreement, highlighting the strategic importance of this collaboration.
A Node That Sets the Standard
According to AMD’s Senior Vice President, “TSMC currently leads the 2 nm process, so we are focusing our development and production efforts on this node to maximize the efficiency and performance of our future chips.” TSMC’s selection is not random; the Taiwanese foundry has solidified its position as a global leader in cutting-edge processes, especially with advancements achieved in the N5 and N3 nodes.
The 2 nm node will use transistors with a Gate-All-Around (GAA) architecture, an evolution from traditional FinFETs, promising substantial improvements in density, energy consumption, and scalability. AMD plans to leverage these advantages in both its data center chips and future consumer processors.
The New EPYC Venice with Zen 6
The first concrete application of this node will be in the sixth generation of EPYC CPUs, codenamed Venice. These chips will be based on the Zen 6 and Zen 6C architectures and could feature up to 8 chiplets (CCDs), 96 standard cores, and up to 256 dense cores in their most advanced variants. Additionally, each CCD could integrate up to 128 MB of L3 cache, a significant leap from previous generations.
These specifications position the Venice chips as strong contenders to lead the server market, a sector where AMD has already gained a growing share against Intel in recent years. In fact, the company reported a 57% increase in its data center business during Q1 of 2025, driven by the adoption of its solutions in enterprise and AI infrastructures.
An Open Door for Samsung?
Despite its public backing of TSMC, AMD does not rule out diversifying its supply chain. The company’s vice president hinted that they are in discussions with multiple technology partners, with Samsung Foundry being a strong candidate to become a second supplier.
Samsung is also developing its own 2 nm technology and has already presented advancements in GAA integration. Furthermore, the South Korean company could offer more competitive pricing, a factor that could also attract clients like NVIDIA, which is considering options outside TSMC in response to the increasing demand for advanced wafers.
Competition, Sustainability, and the Future
The race for the 2 nm node is one of the most competitive in recent years. Although Intel has promised to regain ground with its “Intel 20A” and “18A” nodes, and Samsung is advancing with its SF2 process, TSMC has managed to stay ahead due to its track record of reliability and performance.
Production costs are also a key factor: the price per 2 nm wafer is expected to exceed $30,000, necessitating optimization at every step of the design and manufacturing process. In this context, AMD’s decision to go with TSMC as its main partner makes sense, though keeping other options like Samsung open reduces risks and ensures sufficient production capacity.
Ultimately, the rollout of the EPYC Venice processors will mark a new turning point for AMD, consolidating its innovation strategy through cutting-edge nodes and positioning it to lead both high-performance computing and energy efficiency.