The new AMD EPYC “Venice” processor marks the beginning of the 2-nanometer era in high-performance computing.
AMD has officially announced that its next generation of data center processors, AMD EPYC “Venice”, has become the first HPC product in the industry to be manufactured on TSMC’s 2-nanometer (N2) technology. This achievement not only represents a significant step forward in the company’s server roadmap but also reflects the strategic collaboration it maintains with TSMC regarding semiconductor innovation.
The announcement also includes the successful validation of 5th generation EPYC products in TSMC’s new manufacturing facilities in Arizona (Fab 21), cementing AMD’s commitment to domestic semiconductor production in the U.S.
A technological leap driven by collaboration
According to Lisa Su, President and CEO of AMD, this milestone reaffirms the company’s position as a leader in high-performance computing innovation:
“Being a leading customer at TSMC’s N2 node and its new Arizona facility are key examples of how our close collaboration enables the creation of advanced technologies that drive the future of computing.”
Meanwhile, C.C. Wei, CEO of TSMC, emphasized the joint impact of this cooperation:
“We are proud that AMD is one of the first customers to utilize our N2 technology. Together, we are achieving significant advancements in performance, energy efficiency, and scalability for high-performance silicon.”
“Venice”: the future of EPYC in 2 nm
The “Venice” processor aligns with AMD’s plan to launch new EPYC chips in 2026 and will be the first HPC product to benefit from TSMC’s N2 process, which offers:
- Higher transistor density, allowing more cores per chip.
- Improved energy efficiency, crucial for cloud and AI environments.
- Superior computational performance, aimed at critical workloads such as artificial intelligence, data science, and scientific simulation.
“Venice” is expected to represent a qualitative leap over the previous generation (EPYC “Genoa” and “Bergamo”), both in energy consumption and computing capacity per watt.
Strengthening the semiconductor ecosystem in the U.S.
In addition to technical innovation, AMD has highlighted its involvement in the U.S. technological reindustrialization strategy, collaborating with TSMC in the validation of products in its new Fab 21 factory in Arizona. This move not only responds to current geopolitical tensions in Asia but also seeks to enhance resilience in the global supply chain.
Conclusion
The milestone achieved by AMD and TSMC with the tape-out of the EPYC “Venice” processor in 2 nm technology marks a new era for high-performance computing. This collaboration promises more powerful, efficient products tailored to the growing demands of data centers, generative AI, supercomputing, and distributed cloud environments.
The industry eagerly awaits the official launch of “Venice” in 2026, which could redefine the standards of performance and efficiency in the data centers of the future.
Source: AMD