Altera’s “pure FPGA” lineup is back on the scene with product muscle and, above all, a strong commitment to making life easier for design teams. During their Innovators Day, the company announced the availability of all Agilex families in production (including Agilex 5 and Agilex 3 SoC FPGAs) and launched Quartus Prime 25.3 with a new Visual Designer Studio aimed at reducing weeks in IP integration. The highlight: a density increase of up to 2.5× in the Agilex 5 D-Series — reaching 1.6 million logic elements —, faster DDR5 and LPDDR5 interfaces, and secure boot with post-quantum cryptography (PQC), a direct nod to sensitive markets (industrial, defense, aerospace, communications, edge AI, or data center).
“Operating as a pure-play FPGA company gives us speed and agility to innovate and respond to market needs,”
said Raghib Hussain, CEO of Altera. “Our investment in channel, ecosystem, and full-stack FPGA tools lowers adoption barriers and enables faster deployment in edge AI and embedded systems with more performance, less latency, and better energy efficiency.”
What’s new in hardware: more capacity, bandwidth, and security
1) Agilex 5 D-Series: up to 2.5× density increase and faster memory
The mid-range D-Series raises the bar with devices reaching up to 1.6 million logic elements (LEs) per chip, a more favorable DSP/LE ratio, and increased memory bandwidth. DDR5 interfaces now hit 5,600 MT/s and LPDDR5 5,500 MT/s per instance (+25% over previous specs). Practically, this enables edge AI inference, 4K/8K video, and 5G/6G radio in compact formats without sacrificing headroom.
2) PQC Secure Boot across the entire D-Series
The Agilex 5 D-Series now feature secure boot with post-quantum cryptography (PQC), building on Altera’s well-known secure design. The dual implication: robustness against today’s threats and resilience against the post-RSA/ECC future when quantum computers become widespread. This is a must-have for defense, aerospace, and critical infrastructure sectors.
3) Agilex 5 and Agilex 3 SoC FPGAs now “in production”
The Agilex 5 and Agilex 3 lines with integrated ARM subsystems are now in production. They are natural candidates for low-latency HW/SW co-processing and power-/cost-optimized embedded AI deployments (industrial control, vision, robotics, audio/video, light automotive).
What’s new in software: Visual Designer Studio and shorter compile times
Quartus Prime 25.3 introduces two advances that directly impact time-to-market:
1) Visual Designer Studio (early access)
Altera’s fourth-generation system integration tool features a “drag-and-drop” interface centered on a block diagram view, allowing placement of IP and RTL and visual inspection of data routes. Its engine suggests valid connections based on design requirements and automatically applies correct wiring, automating much of the logical connectivity.
- Declared benefit: reduces design start-up from 5 days to around 2 hours compared to RTL-only workflows.
- Target users: teams integrating proprietary, commercial IP, hard blocks, soft cores, and RTL designs that previously faced integration challenges.
2) More efficient compilation and fit
Version 25.3 reduces compilation times by about 6% compared to 25.1.1, with a 27% cumulative improvement since Quartus 23.1 (when Agilex 7 entered production). Additionally, designs typically use about 6% fewer ALMs but maintain high Fmax. Simply put, this means more logic density in the target device and fewer iterations to meet timing—a real advantage when resources are tight.
Note: Results depend on the specific design; however, the trend—faster compilations, fewer resources, and fewer iterations—points to a shorter verification cycle.
Implications for edge AI, vision, video, and radio
The increased density and memory bandwidth in Agilex 5 D-Series broaden the range of models and resolutions that can inhabit a single chip with deterministic latency:
- Edge AI/inference: more MACs and DSPs for small/medium CNNs/Transformers without migrating to ASICs or GPUs, offering advantages in latency and power consumption.
- 4K/8K video: more processing resources + faster LPDDR5/DDR5 = streamlined pipelines for processing, scaling, and blending with margin.
- 5G/6G: increased capacity for complex PHY/L1 functions (beamforming, massive MIMO, channel coding) in a compact form factor.
The post-quantum secure boot (PQC) also fits here: firmware and FPGA bitstreams guaranteed to resist future manipulations, valuable in remote cells, vehicles, and hard-to-access infrastructure.
Table | Agilex 5 D-Series: capacity evolution
| Aspect | Before | Now (25.3 / new D-Series) | Impact |
|---|---|---|---|
| Logic density | ≤ ~650–700 k LEs (per device) | Up to 1.6 million LEs | Larger designs without partitioning |
| DDR5 / LPDDR5 | ~4,480–4,800 MT/s (previous spec) | DDR5 5,600 MT/s / LPDDR5 5,500 MT/s | +25% throughput per instance |
| Secure boot | Classic secure design | PQC secure boot | Post-RSA/ECC resilience |
| Quartus compile | Reference 25.1.1 | -6% vs 25.1.1 / -27% vs 23.1 | Faster iterations |
| Average ALM usage | Reference 25.1.1 | -6% vs 25.1.1 | More logic per device |
Ecosystem: ASAP and FPGA AI Suite 25.3
Altera highlighted the strength of the ASAP (Altera Solution Acceleration Partner) program with over 300 registered partners (IP, software, hardware, design services). According to the company, working with approved partners can reduce time to market by up to 50% for complex projects. Additionally, FPGA AI Suite 25.3 was released to accelerate AI model integration in FPGAs (network compilation, resource mapping, runtimes).
What’s in it for design teams? (and what to watch closely)
Less “glue,” more product. Visual Designer Studio automates valid connections between IP, aids in tracing data pathways, and reduces start-up hours. Alongside shorter compilation times and fewer ALMs, this speeds up bring-up, provides room for feature iteration, and shortens project schedules.
Security that adds value. The PQC layer protects boot today and guards against future quantum attacks. For regulated or long-lifecycle sectors, this is a competitive edge.
Flow discipline matters. Even with drag-and-drop, complex projects excel if teams effectively manage versioning, IP management, bitstreams, and hardware CI. Visual Designer accelerates the process but does not substitute disciplined design practices.
Key points to monitor:
- Availability of the densest devices (supply, lead times).
- 成熟度 of Visual Designer Studio (early access today): supported formats, robustness of auto-connections, integration with existing workflows.
- Benchmarks: validate compilation and ALM savings within your own environment.
Conclusion
Altera is executing a “frictionless FPGA” strategy: increasing capacity and bandwidth where needed (edge AI, 8K video, 5G/6G), fortifying boot security with PQC, and reducing cycle times with faster compilation (Quartus) and an IP integration task converter (Visual Designer). For resource- and deadline-constrained teams, these advancements can be what transforms a prototype into a product.
Frequently Asked Questions
Which Agilex devices are already in production?
Altera confirms the full production of all Agilex families, including Agilex 5 and Agilex 3 SoC FPGAs (with integrated ARM subsystem).
How much does Visual Designer Studio actually improve over pure RTL flows?
In early access, Altera claims it reduces design start-up from about 5 days to around 2 hours in typical IP integration scenarios; your results will vary based on complexity and IP/RTL mix.
What does “secure boot PQC” mean in Agilex 5 D-Series?
It indicates that device boot incorporates post-quantum algorithms (besides classical ones), bolstering integrity and authenticity verification against present and future threats.
Is there an objective improvement in compilation in Quartus 25.3?
Yes: about -6% in compilation times versus 25.1.1, with a -27% trend since 23.1; designs typically use around 6% fewer ALMs while maintaining high Fmax. Exact numbers will depend on the specific design.
via: altera