The demand for AI chips continues to grow and is already making a tangible impact on the front lines of manufacturing. According to early press reports in Taiwan, TSMC is preparing a “dizzying” increase in its 3 nm (N3) capacity to largely accommodate NVIDIA’s orders ahead of its next AI platform, internally known as Vera Rubin. This move coincides with the ramp-up of the current Blackwell Ultra and the major computing clients demanding more supply.
The picture painted by these developments is clear: N3 will go from about 100,000 wafers per month to approximately 160,000 at the Tainan (Southern Taiwan Science Park) plant, representing a 45–50% increase. A significant portion — reports talk of a “large exclusive share” — would be reserved for NVIDIA, which is securing slots months in advance to avoid the same bottleneck that has challenged the industry since 2023. Jensen Huang, the CEO of the company, recently traveled to Taiwan to visit the 3 nm facility and meet with TSMC’s leadership.
Why 3 nm (N3P) is the new battleground
“Rubin” isn’t a minor update. The roadmap points to cross-architecture improvements and a move to N3P, TSMC’s refined 3 nm process variant, aiming to boost density, energy efficiency, and frequencies. The platform is also tied to the upcoming HBM4, the next generation high-bandwidth memory that will continue to push training and inference performance in data centers. Collectively, the package promises more computation per watt and larger memory capacities, two variables that, today, dominate AI farms.
For NVIDIA to reserve wafers now aligns with a pattern recurring throughout the supply chain: major suppliers are protecting themselves against a 2026 that will be intensive in AI inference, scale-out serving, and multi-cluster training. Each passing quarter, TSMC cements HPC/AI as the driver of its revenue, with N3 becoming its backbone for several quarters, in anticipation of the transition to A16 (≈1.6 nm) later in the decade.
The key figure explaining the sense of urgency: 35,000 wafers/month just for NVIDIA
Local press details indicate that Tainan’s 18B facility will expand from about 10–11 wafer starts (×10,000) to 16 wafer starts, with NVIDIA attributed approximately 35,000 wafers/month for its 3 nm AI dies. This volume would coexist with the final stages of Blackwell Ultra and preparations for Vera Rubin expected around mid to late 2026, aligning with plans by hyperscalers to renew clusters and transition to HBM4.
If this allocation is confirmed, TSMC’s 3 nm mix will become even more skewed toward HPC/AI, relegating mobile and PC clients that have been vying since 2023 for N3 and N4 slots. It’s not an anomaly: it’s the new normal. Per-wafer revenues in HPC surpass almost any other segment, and the average lot size for an AI accelerator is tied to multi-year contracts worth hundreds or thousands of millions.
Packaging, another bottleneck not to be ignored
Beyond process technology, advanced packaging continues to impose limits. Technologies such as CoWoS, InFO, and their evolutions for HBM4 have been the true bottleneck in the 2023–2024 AI ramp-up. Increasing wafer starts is necessary but not sufficient: capacity for testing, assembly, and substrates must also expand. The good news for NVIDIA is that TSMC has already been expanding its manufacturing facilities and OSAT ecosystem; the downside is that p99 availability is determined by packaging when everyone demands capacity simultaneously.
Implications for the broader landscape
- For TSMC: N3 will strengthen its revenue share over several quarters. The company reaffirms its role as a system partner for AI: without its 3 nm ramp-up (and packaging), the “token economy” doesn’t scale.
- For Samsung Foundry and Intel Foundry: the race isn’t over, but the move narrows the margin. In the short term, the most realistic option for capturing NVIDIA’s load involves packaging and complementary nodes; on the leading node, inertia favors TSMC.
- For hyperscalers: securing capacity commitments before 2026 will be the difference between launching and delaying. Those who haven’t secured wafers and HBM4 will need to adjust timelines or architectures.
- For the AI competition: if Rubin delivers the expected leap, the window to close the gap with NVIDIA narrows. Catch-up will depend on both software (compilers, runtimes, libraries) and silicon.
Why Jensen is in Taiwan (and why this is more than just a photo)
Beyond the symbolic gesture — participating in TSMC’s internal event and posing with its leadership — the visit has a clear agenda: capacity, timelines, and prioritization. NVIDIA is currently TSMC’s key anchor client for HPC, and it needs visibility to align its roadmap with multimillion-dollar contracts from hyperscalers already in multi-cloud and multi-year modes. Huang’s message during his visit to the island was unmistakable: the business is “very strong” month by month, and Taiwan is critical to maintaining that rhythm.
Unseen risks: energy and costs
The 3 nm ramp cannot be sustained without megawatts. Taiwan, the U.S., and Europe simultaneously face surges in electrical demand for data centers and fabs. Underestimating the energy equation was the mistake of 2023 in cloud infrastructure; repeating it in manufacturing would be even worse. If the cost per watt increases or supply becomes strained, timelines stretch and capex rises. TSMC has been cautious in its expansion, but the scale demanded by AI forces long-term planning with years of margin.
When will Rubin appear on real machines?
Foundry timelines suggest early silicon samples by the first half of 2026, with production targeted for late 2026 and deployment visible in 2027. Meanwhile, Blackwell Ultra will continue driving progress, with cluster expansions already committed for 2025–2026. The most aggressive hyperscalers will operate in overlaps: expanding Blackwell while preparing for Rubin’s arrival.
Executive summary in 60 seconds
- TSMC plans to increase its 3 nm capacity by about 50% (from around 100,000 to 160,000 wafers/month) at Tainan to primarily serve NVIDIA.
- NVIDIA has secured approximately 35,000 wafers/month of N3P for its next-gen “Vera Rubin”, which will combine 3 nm node and HBM4.
- The main constraint will continue to be in advanced packaging; CoWoS and its successors define the p99 availability.
- Likely timeline: Rubin appears in 2026; Blackwell Ultra extends its cycle through 2025 and into parts of 2026.
via: udn