Intel took advantage of Hot Chips 2026 to showcase in greater detail Diamond Rapids, the next-generation Xeon processors for servers. The company confirms a configuration of up to 256 performance cores, 1.28 GB of last-level cache, 16 memory channels, and 128 PCIe 6.0 lanes, a combination aimed at strengthening its position in data centers as competition from AMD, Arm, and processors designed by hyperscalers continues to grow.
The key points of Intel Diamond Rapids in 20 seconds
- Diamond Rapids will arrive in 2027 as the next generation of Intel Xeon.
- The top configuration will reach 256 cores and 1.28 GB of LLC cache.
- It will feature 16 memory channels, DDR5-8000, and MRDIMM up to 12,800 MT/s.
- It will incorporate 128 PCIe 6.0 lanes and CXL 3.0.
- Intel will use its 18A-P process and advanced Foveros Direct 3D packaging technology.
The presentation held on August 24 also clears up one of the uncertainties surrounding the processor. Previous information placed the maximum at around 192 cores, but Intel has shown a configuration reaching up to 256 cores at Hot Chips. This change is especially significant in light of AMD’s upcoming EPYC generation and the increasing availability of Arm CPUs for data centers.
Diamond Rapids will also be an important test for Intel Foundry. The compute chiplets will utilize Intel 18A-P, an evolution of the 18A process on which the company is heavily investing to recover its technological competitiveness in semiconductor manufacturing.
Intel positions the new Xeon within a broader strategy for artificial intelligence. At Hot Chips, it also introduced the Crescent Island GPU for inference and its Wildcat Lake architecture for client devices and edge computing. But Diamond Rapids has a different mission: to keep the x86 CPU relevant in servers where much of the investment growth is focused on accelerators.
Up to 256 cores and a more complex chiplet architecture
The top configuration announced by Intel combines four compute blocks and reaches 256 cores. The processor also features up to 1.28 GB of last-level cache (LLC).
Its design demonstrates how server CPUs have become systems composed of multiple silicon pieces.
The shown packaging at Hot Chips integrates two Fabric Hub Tiles, 16 core chiplets, and four base tiles. The compute chiplets connect to the lower tiles via Foveros Direct, Intel’s direct chip-to-chip bonding technology.
Fabric Hubs play a crucial role by centralizing much of the processor’s communications. Each also has up to 16 MB of I/O cache and two accelerator complexes with technologies like Intel QuickAssist Technology (QAT), Data Streaming Accelerator (DSA), and In-Memory Analytics Accelerator (IAA).
Intel has also physically reorganized the processor compared to previous generations. The architecture shifts compute blocks to the sides while concentrating memory and I/O in other areas of the package.
This modular approach enables building different configurations by reusing common blocks, a strategy AMD has long exploited with its chiplet-based EPYC processors.
Diamond Rapids also introduces new instructions called spill-and-fill optimization instructions. Changes include expanding from 16 to 32 general-purpose integer registers and adding new three-operand instructions. Intel maintains compatibility with existing x86 software, although some applications will need recompilation to leverage the new capabilities.
Memory will be a key weapon for Diamond Rapids
Core count is only part of the story.
Intel is dedicating significant focus to memory bandwidth, which is increasingly vital for databases, high-performance computing (HPC), virtualization, and certain AI workloads.
Diamond Rapids will feature 16 DDR5 memory channels, compared to lower configurations used in earlier generations.
The platform will support DDR5 up to 8,000 MT/s and second-generation MRDIMM modules capable of reaching 12,800 MT/s.
MRDIMM (Multiplexed Rank Dual Inline Memory Module) uses multiple memory ranks working in coordination to boost transfer rates to the controller. For Intel, this technology significantly increases bandwidth without resorting to specialized memory like HBM.
Connectivity is also advancing.
Diamond Rapids will provide 128 PCI Express 6.0 lanes, along with support for Compute Express Link (CXL) 3.0 and UPI 3 for inter-processor communication. It also includes eight PCIe 4.0 lanes.
CXL can be especially relevant in large servers, enabling memory and accelerator connections via a coherent architecture. The ability to expand or share memory resources is becoming more important as datasets in AI applications grow.
Intel has also enhanced power management. Diamond Rapids incorporates new low-power states that can retain L2 cache, mechanisms to prioritize specific cores in turbo mode, and improvements in memory thermal management.
Intel needs more than many cores
Diamond Rapids will arrive at a particularly challenging time for Intel.
Recent Mercury Research data for Q2 2026 shows AMD reaching approximately 34.5% of x86 CPU units for servers, compared to Intel’s 65.5%. The gap widens when adjusting for certain reporting differences between the data center products of both companies.
At the same time, the competition isn’t limited to AMD anymore.
AWS develops Graviton, Google has Axion, Microsoft offers Cobalt, NVIDIA is entering with Vera, and Qualcomm is preparing its return to server processors. Arm also showcased its AGI architecture based on chiplets at Hot Chips, while Fujitsu introduced MONAKA. The conference agenda itself reflects how diversified the market has become.
AI is accelerating this transformation. Large data center operators can justify the development of custom silicon when deploying hundreds of thousands of servers and knowing the specific workloads they’ll run.
Intel’s approach combines general-purpose CPUs with accelerators and specialized architectures.
It defines Diamond Rapids as a platform for orchestrating enterprise and AI workloads, reserving Crescent Island for inference. The goal is for CPU, GPU, and other accelerators to collaborate within the same data center, rather than focusing solely on GPU-based AI.
Intel is also collaborating with NVIDIA on a custom Xeon integrated with NVLink, confirmed as part of its strategy for AI nodes.
Diamond Rapids will also need to prove the competitiveness of Intel 18A-P.
According to Intel, this process is designed to deliver about 9% more peak performance than 18A or reduce power consumption by roughly 18% while maintaining the same performance. These are manufacturer estimates; real-world results in servers will only be known once products are available.
The timeline presents another challenge. Intel now estimates Diamond Rapids in 2027, even as the data center CPU market continues to advance rapidly. The company has indicated that afterward, it will introduce Coral Rapids, which aims to recover multithreading capabilities in its server architecture.
That’s why the 256 cores shown at Hot Chips are noteworthy but insufficient alone to determine the product’s competitiveness. Factors like per-core performance, power efficiency, price, availability, effective memory bandwidth, and rack performance will also be crucial.
Diamond Rapids indicates that Intel is preparing a significantly more ambitious Xeon. The ultimate answer will come once these processors can be compared in commercial systems against upcoming EPYC chips, new Arm CPUs, and the custom silicon deployed by top cloud operators in their own data centers.
Frequently Asked Questions
How many cores will Intel Diamond Rapids have?
Intel has demonstrated configurations of up to 256 cores at Hot Chips 2026, accompanied by up to 1.28 GB of last-level cache.
When will Diamond Rapids be released?
Intel targets 2027 for the launch of its next-gen Xeon Diamond Rapids. The company has not yet specified an exact commercial release date.
What memory will Diamond Rapids use?
The platform will feature 16 memory channels and support DDR5 up to 8,000 MT/s, along with second-generation MRDIMMs reaching 12,800 MT/s.
Will Diamond Rapids use Intel 18A?
Yes, the compute chiplets will utilize Intel 18A-P, an evolution designed to improve performance and efficiency compared to the original 18A process.
