Rapidus has taken a new step in its efforts to become an alternative in the global advanced semiconductor manufacturing market. The Japanese company will integrate Cadence’s AI agent InnoStack into its RAADS design platform, with the declared goal of reducing the time required to bring a system-on-chip (SoC) from initial architecture decisions to pre-fabrication verification by up to 50%.
The key points of Rapidus’s strategy in 30 seconds
- Rapidus will incorporate Cadence’s AI agent into its RAADS platform to coordinate various phases of chip design.
- The company aims to double the speed of design cycles compared to traditional flows.
- Its approach combines 2-nanometer logic fabrication, intellectual property for HBM4, and high-speed interconnects.
- 2.5D and 3D packaging are part of the offering aimed at the AI accelerator market.
- Mass production of its 2-nanometer process is still scheduled for 2027.
This agreement goes beyond using artificial intelligence to adjust some design parameters. Cadence and Rapidus intend for the system to decide which electronic design automation (EDA) tools to run, coordinate their results, and determine subsequent steps for much of the process.
This approach addresses an increasingly complex challenge. Advanced chip design is no longer done as an isolated block. Engineers must balance performance, power consumption, area, temperature, signal distribution, memory, interconnects, and manufacturability options. Changes in any of these areas may require re-analysis and revisions elsewhere.
The promise of the AI agent is to reduce some of this repetitive work. Rapidus claims up to a twofold improvement in design response time, though this remains a goal rather than a proven performance metric in commercial projects.
RAADS aims to coordinate full chip design
The Rapidus AI-Agentic Design Solution platform, called RAADS, is part of the foundry model that the Japanese company is building around its upcoming 2-nanometer technology.
Cadence will incorporate InnoStack AI Super Agent into this platform, which is designed to coordinate tools used at different stages of SoC development. Its scope includes from initial architecture exploration to physical implementation and signoff, the final verification step to determine if the design is ready for manufacturing.
In conventional flows, engineers run specialized tools to place blocks within the chip, connect their elements, analyze power consumption, check timing, and verify process rule compliance.
AI-based systems could already assist with specific tasks. The difference with Rapidus and Cadence lies in coordination. The agent can select tools, analyze results, and propose new executions without waiting for manual configuration by humans.
Rapidus has also expanded RAADS with two components called Navigator and Indicator. These tools help identify problems, monitor design quality, and assist teams in resolving issues before entering phases where changes are much more costly.
Previously, in 2025, the company introduced other parts of this platform, such as RAADS Generator, which generates RTL designs from specifications, and RAADS Predictor, which anticipates performance, power, and area metrics before completing physical design.
Integration with Cadence makes these functions part of a broader proposal. Rapidus does not want to merely provide a design kit for clients to work independently. Its goal is to support design, manufacturing, and packaging within a unified environment.
The 2-nanometer node is just part of the plan
The most visible element of Rapidus continues to be its 2-nanometer process with gate-all-around (GAA) transistors. Based on work developed with IBM, this technology is being implemented at the IIM-1 factory in Chitose, Hokkaido.
Rapidus succeeded in 2025 to produce prototypes of 2nm GAA transistors and obtained their first electrical characteristics. The next challenge is to translate these lab and pilot results into a stable, repeatable process with sufficient yields for commercial customers.
Mass production is scheduled for 2027. Meeting this timetable requires completing the design kit, validating libraries, qualifying IP, improving yields, and demonstrating that designs can transition from EDA tools to functional silicon without lengthy correction cycles.
The company is late in a race where TSMC, Samsung, and Intel already have large ecosystems of customers, suppliers, and tools. Therefore, Rapidus seeks to differentiate not only by the node but also by the speed with which it can handle specific designs.
Its Rapid and Unified Manufacturing Service (RUMS) model emphasizes short cycles, wafer-by-wafer processing, and intensive data use to optimize production. The factory records information on each wafer to refine processes and anticipate deviations.
Applying AI to design aligns with this approach. If RAADS can connect tool data with actual manufacturing characteristics, Rapidus might reduce the gap between chip designers and fabrication teams.
HBM4 and high-speed interconnects for AI accelerators
Rapidus’s strategy also links its 2nm logic technology with high-bandwidth memory (HBM4) and interfaces essential for building AI accelerators.
Previous collaborations with Cadence include access to IP for HBM4, 224 Gbps SerDes links, and PCI Express 7.0. These components matter because the performance of modern accelerators depends on both compute units and data transfer speeds.
HBM memory is placed near the processor using advanced packaging and offers bandwidth far superior to conventional memory. It is a critical component in GPUs and ASICs used for training and deploying large AI models.
Rapidus has not announced plans to manufacture HBM itself. Its expertise is in advanced logic. It aims to create an environment where the compute chip can be designed with interfaces ready to communicate with HBM4 and other components within the same package.
This distinction is important. The goal is not to integrate all memory stages in a single fab but to enable clients and partners to combine logic, memory, and interconnects in complete systems.
The internal server network also plays a role. High-speed interfaces allow connecting accelerators, CPUs, memory, and I/O devices without data movement negating manufacturing gains.
The AI market has shown that shrinking transistors alone is not enough. A chip with massive compute capacity can underperform if memory, packaging, or communication bottlenecks cannot supply data efficiently.
Advanced packaging becomes part of the foundry offering
Rapidus also aims to participate in chiplet packaging using 2.5D and 3D technologies. Instead of manufacturing the entire system on a single piece of silicon, chiplets divide functions across multiple dies that may use different processes.
An accelerator could combine a 2nm logic chip with input/output blocks built on more mature nodes, plus HBM modules from other suppliers. Packaging handles the assembly, high-density connections, power delivery, signaling, and heat dissipation.
2.5D involves mounting components on an interposer, while 3D stacks them vertically with through-silicon interconnects. Both reduce data travel distance but pose challenges in temperature, fabrication yield, and cost.
Rapidus maintains a collaboration with IBM to develop chiplet encapsulation technologies targeting 2nm. The company also includes interfaces such as HBM, UCIe, and SerDes in its packaging development plans.
This combination clarifies its strategy. Rapidus does not seek to compete solely by providing small transistor chips; instead, it aims to offer an integrated chain encompassing AI-assisted design, advanced logic fabrication, and system assembly with chiplets.
For custom chip clients, reducing the number of vendors and exchanges between design, foundry, and packaging can shorten development cycles. However, it also increases Rapidus’s responsibility to demonstrate quality across multiple complex areas simultaneously.
An ambitious proposal still searching for customers
Japan’s financial support has enabled Rapidus to build an advanced factory and establish agreements with IBM, Cadence, Synopsys, and other partners. Initial shareholders include Toyota, Sony, SoftBank, Kioxia, NTT, NEC, Denso, and MUFG Bank.
Funding addresses part of the challenge, but a foundry needs clients willing to entrust their most valuable designs to a new process. Leading chip developers typically evaluate node stability, yields, IP availability, and delivery capacity over several years.
Integrating InnoStack into RAADS aims to reduce that risk at the design stage. If the environment can identify problems earlier and adapt the chip design quickly to manufacturing rules, clients might perform initial tests with fewer resources.
The goal of halving design time reflects a joint program target. Actual results will depend on SoC complexity, library maturity, data quality, and the amount of human intervention still required.
Rapidus does not yet operate at TSMC or Samsung scale. Its opportunity lies in providing shorter cycles and tailored support for companies designing ASICs, AI accelerators, or high-performance products in smaller volumes or with specific needs.
The partnership with Cadence reinforces this direction. While 2nm nodes garner attention, competition in foundry services increasingly hinges on everything around transistors: tools, libraries, memory, interconnects, chiplets, packaging, and rapid design iteration.
Frequently Asked Questions
What has Rapidus announced with Cadence?
The two companies will integrate Cadence’s InnoStack AI agent into Rapidus’s RAADS platform to automate and coordinate various phases of SoC design.
When will Rapidus start manufacturing 2nm chips?
Rapidus aims to begin volume production in 2027. While prototypes of 2nm GAA transistors have been created, full industrialization of the process is still underway.
Will Rapidus manufacture HBM4 memory?
No, Rapidus has not announced HBM4 fabrication. Its strategy is to provide advanced logic, interface IP, and packaging solutions to enable integration with HBM memory from other suppliers.
What advantage does advanced packaging offer?
It allows combining different chiplets and memory components within a single package, reducing data travel distance and enabling the use of the most suitable manufacturing processes for each function.
via: rapidus
