Rapidus aims to enter advanced semiconductor manufacturing with an irresistible proposal: producing 2-nanometer class wafers for between 3 and 3.5 million yen, roughly $18,500 to $21,600 at current exchange rates. The Japanese manufacturer plans to start volume production in the second half of 2027 and compete with TSMC and Samsung through competitive pricing, shorter fabrication cycles, and a service tailored to specialty chips.
Rapidus’s plan essentials in 20 seconds
- Target price: between 3 and 3.5 million yen per 300mm wafer.
- Approximate equivalence: around $18,500 to $21,600, depending on the exchange rate.
- Timeline: volume production during the fiscal year 2027.
- Technology: 2HP 2nm process with GAA nanosheet transistors.
- Factory: IIM-1 facility in Chitose, on Japan’s Hokkaido island.
- Differentiation: individual wafer processing throughout all front-end stages.
- Potential clients: the company is in talks with more than 60 firms.
- Main uncertainty: still needs to demonstrate manufacturing performance, capacity, and sustainable cost at a commercial scale.
Atsuyoshi Koike, President of Rapidus, explained that the company will benchmark TSMC’s prices and aim to match or slightly undercut them. The executive acknowledged that a company not yet producing commercial chips lacks the leverage to set its own rates and must adapt to the market established by the Taiwanese foundry.
The range of 3 to 3.5 million yen should be seen as a business target, not a definitive rate. Price will depend on design complexity, contracted volume, mask requirements, testing, packaging, IP agreements, and the factory’s performance.
It’s also unclear whether Rapidus will charge one-third less than TSMC, as some reports suggest. Industry sources quote TSMC’s N2 wafer around $30,000 and Samsung’s SF2 technology close to $20,000. However, The Japan Times assigns TSMC’s reference price at 3 to 3.5 million yen, almost identical to Rapidus’s announced range.
TSMC does not publish official price lists for its advanced nodes. Contracts are negotiated privately and can vary greatly depending on whether a customer orders tens of thousands of wafers or a limited series. Therefore, the estimates of $20,000 vs. $30,000 derive from industry approximations, not verified official rates.
A cheaper wafer doesn’t always mean cheaper chips
Wafer cost is only part of the actual expense of a semiconductor. What matters to the designer is how much they pay per functional chip at the end of the process.
A 300mm wafer can hold anywhere from dozens of large processors to thousands of tiny circuits. The final cost depends on design size, edge lost space, and especially the number of units that pass testing successfully.
If Rapidus sells a wafer for $20,000 but achieves a 50% yield, the cost per usable chip could be higher than that of a $30,000 wafer from TSMC with an 80% yield. Defect rates are particularly critical for large AI processors, networking, or server chips, as even a single anomaly can render a substantial silicon area unusable.
TSMC began volume production of its N2 technology at the end of 2025. By the time Rapidus enters the market in late 2027, its rival will have accumulated about two years of industrial experience with GAA transistors, multiple process iterations, and data from numerous commercial products.
The Taiwanese foundry will also be deploying later versions of its platform. TSMC has expanded the 2nm family with N2P and is preparing variants like N2U for 2028. The company describes N2U as an evolution that benefits from the maturity and manufacturing performance already achieved by the N2 platform.
Rapidus will start from a different baseline. In July 2025, it succeeded in fabricating its first prototype GAA transistors at IIM-1, confirming expected electrical characteristics. While a significant technical milestone, there is still a considerable gap between producing test structures and manufacturing full, profitable processors for months.
The company must finalize its design kit, validate libraries, run test chips for clients, and demonstrate repeatability across wafers. It will also need to secure equipment, materials, photomasks, and skilled personnel.
Therefore, launching full-scale production in 2027 doesn’t mean Rapidus will immediately supply tens of thousands of wafers per month. New fabs usually start with reduced volumes that increase as defects are corrected and processes stabilize. It’s reasonable to expect the most significant commercial impact in 2028, depending on yield achievements.
Individual wafer processing as its key differentiator
Rapidus plans to stand out by processing each wafer individually at every front-end step. In conventional fabs, some operations are performed in batch mode, with multiple wafers processed simultaneously on certain equipment to boost throughput and reduce costs per unit.
The Japanese approach treats each wafer separately. This allows collecting more detailed data, quickly adjusting parameters, and responding faster to deviations. Rapidus aims to use this information to automate the factory and shorten the time from wafer entry to completion.
This strategy might appeal to companies developing moderate-volume custom chips. An AI accelerator designer, robotics processor, automotive, or networking infrastructure firm could value faster turnaround over the absolute lowest price for millions of units.
This model differs somewhat from TSMC’s high-volume approach, which focuses on producing enormous quantities for clients like Apple, Nvidia, AMD, Qualcomm, while maintaining very stable processes.
Individual wafer processing also has a downside: it can reduce equipment utilization. Tools working on a single wafer at a time require more operations to produce the same volume as batch processing. Time savings and flexibility must compensate for this lower efficiency.
Rapidus believes automation and real-time monitoring will help control costs. The company intends to detect anomalies during fabrication and adjust parameters on subsequent wafers without waiting for entire batches to complete.
While suited for high-value series, this approach still needs to prove it can charge around $20,000 per wafer without incurring losses. 2nm fabs require EUV equipment, deposition and etch systems, metrology, ultra-pure materials, and an infrastructure that consumes large amounts of electricity and water.
The Japanese government has approved over 2.35 trillion yen in support for Rapidus’s R&D efforts. The company has also secured funding from Toyota, Sony, SoftBank, Denso, Kioxia, Canon, and Fujitsu. Public backing allows taking an initial phase that would be difficult for a startup to finance solely through revenue.
This aid alleviates immediate financial pressure but doesn’t eliminate the need to build a sustainable business. Japan aims to regain industrial capacity in a strategic activity, while Rapidus must turn this public policy into recurring commercial orders.
The ecosystem will be as important as the process itself
TSMC’s leadership in contract manufacturing is partly due to its Open Innovation Platform, which includes electronic design tools, IP libraries, design companies, cloud services, substrate makers, and advanced packaging technologies.
Customers can access verified CPU cores, memory controllers, PCIe interfaces, security modules, and other components tailored for specific nodes. Reusing proven IP shortens development time and reduces the risk of failure in multi-billion-dollar chips due to integration errors.
Rapidus will have to offer a similar environment, even if initially smaller. Its partnership with IBM provides the technological foundation for GAA transistors, while collaboration with imec brings expertise on advanced processes. But technology transfer alone doesn’t automatically create a full library of IP and tools.
More than 60 potential clients are reportedly in negotiations, but conversations are not same as orders. Before committing to a major processor, each company will assess the PDK, performance, library availability, packaging options, and supply guarantees.
Rapidus might find opportunities among those unable to secure enough capacity at TSMC or seeking to diversify outside Taiwan. Proximity to Japanese clients in automotive, robotics, telecom, and electronics markets could also be advantageous.
Technological sovereignty is another factor. Japan relies on foreign manufacturers for its most advanced processors and sees this concentration as a strategic risk. A domestic foundry could retain some knowledge and production within the country.
However, geopolitics alone don’t guarantee competitive products. Customers will continue to compare performance, power consumption, density, cost per usable chip, and punctuality. Subsidized fabs may attract initial designs, but ongoing success depends on delivering results.
Rapidus is already thinking ahead to future generations. The company plans to develop a 1.4nm process and aims to start production around 2029, possibly with a second facility in Chitose. Meanwhile, TSMC has announced A14 for 2028 and A13 for 2029, along with evolutions of its 2nm platform.
The race won’t be decided solely by who announces the smallest number. Names like 2nm, 1.8nm, or 1.4nm are generational designations, not literal transistor dimensions. Different manufacturers use distinct designs, libraries, and rules, so nodes with similar names can differ significantly in density and capabilities.
Rapidus has a real chance to become an alternative for certain advanced chips. Its target price is competitive, individual processing may shorten timelines, and Japan is willing to fund the project. The biggest challenge remains: proving it can produce thousands of wafers with stable yields when TSMC is already working on the next evolution of its technology.
Frequently Asked Questions
How much will a 2nm Rapidus wafer cost?
The company is considering a price between 3 and 3.5 million yen, approximately $18,500 to $21,600. The final rate depends on the customer, design, volume, and additional services.
Will it really be cheaper than TSMC?
Rapidus aims to match or slightly undercut TSMC’s prices. Some estimates place TSMC’s N2 wafers at around $30,000, but other sources suggest a similar range to Rapidus’s. TSMC does not publish official pricing.
When will Rapidus start manufacturing commercial chips?
The goal is to begin volume production in the second half of 2027. The ramp-up to substantial volumes will likely be gradual.
What is the advantage of individual wafer processing?
It allows for controlling and adjusting each chip separately, gathering more detailed data, and potentially reducing manufacturing cycles. However, it may lead to lower equipment utilization compared to batch processing.
via: Japan Times
