Intel is making another move in the battle to regain credibility as an advanced chip manufacturer. According to supply chain information gathered by TrendForce from ETNews, the company is exploring an evolution of its Intel 14A node, provisionally known as 14A2, featuring a power architecture that covers both sides of the chip: from the back and also from the front. Intel has not officially announced this 14A2, so it should be considered a work in progress rather than a confirmed roadmap.
This news matters because the foundry market is approaching a particularly tough phase. TSMC is preparing its A14 node for production in 2028, Samsung aims to start mass production of SF1.4 in 2029, and Intel wants 14A to prove that its third-party manufacturing business can compete at the top tier of technology. At this stage, the competitive edge is no longer just about “nanometers,” a label increasingly used for marketing, but about transistors, power delivery, lithography, density, performance, power consumption, and the actual ability to produce at scale.
What would change with Intel 14A2
The Intel 14A node is already ambitious on its own. The company describes it as a generational evolution featuring RibbonFET 2 gate-all-around transistors and PowerDirect, its technology for delivering power from the back side of the chip. According to Intel Foundry, 14A aims to deliver between 15% and 20% higher performance at the same power, or 25% to 35% less power at the same performance, plus up to 30% higher density compared to Intel 18A.
Delivering power from the back side, or backside power delivery, separates part of the power lines from the signal lines. In traditional chips, power and signals compete for space on the front side. Moving power to the back side frees space, reduces voltage drop, and enhances efficiency. Intel already introduced PowerVia in 18A and envisions PowerDirect as a more advanced step in 14A.
The purported novelty of 14A2 would lie in not relying solely on the back side. The dual-sided architecture would combine back-side power delivery with some auxiliary power or distribution from the front. According to TrendForce, the goal is to address issues that arise when further reducing the M0 pitch, the minimum spacing associated with the finest metal layers. The base 14A might target around 28 nm, while 14A2 could attempt to go down toward 21 nm.
This leap could increase density but wouldn’t come without cost. Narrower interconnects increase resistance and complicate power delivery, signal control, and physical design. Therefore, a hybrid architecture with the back side as the primary route and the front side as support might make sense technically. The key question is whether it also makes sense from a cost, manufacturing performance, and customer adoption perspective.
Pressure from TSMC and Samsung
Intel is not designing 14A in isolation. TSMC announced its A14 process in 2025 as the next logical generation after N2, with volume production expected in 2028. The Taiwanese company promises up to 15% higher speed at the same power, up to 30% lower power at equivalent performance, and over 20% increase in logic density compared to N2.
TSMC’s strategy differs from Intel’s. While Intel is betting on High-NA EUV for 14A, TSMC has argued that it can bring A14 into volume production without needing High-NA EUV at that stage. For its customers, this could mean less technological transition risk if the company can maintain performance, density, and costs with current EUV tools and design optimization.
Meanwhile, Samsung has adjusted its timeline. According to The Elec, the company reaffirmed at the SAFE Forum 2026 that its SF1.4 process targets mass production in 2029 for leading customers, with an improved version, SF1.4+, arriving in 2030. Initially, Samsung had planned an earlier arrival but has prioritized stabilizing and improving its 2 nm nodes before making the jump.
The current landscape looks like this:
| Manufacturer | Node Class 1.4 nm | Reported or Announced Timeline | Key Technologies |
|---|---|---|---|
| Intel | 14A | 14A in development; 14A2 reported, not official | RibbonFET 2, PowerDirect, High-NA EUV |
| TSMC | A14 | Volume production planned for 2028 | Nanosheet, NanoFlex Pro, volume optimization without High-NA EUV |
| Samsung | SF1.4 | Mass production expected in 2029 | GAA evolution, prior focus on stabilizing 2 nm |
This comparison should be approached with caution. The names 14A, A14, or SF1.4 do not imply that all processes have the exact same physical dimensions. Each foundry uses different rules, libraries, densities, transistors, metallization, and packaging technologies. What matters most is not just the number but the performance, power consumption, cost, and reliability each node delivers.
High-NA EUV: technological advantage and economic risk
Intel aims to position itself as the first major user of High-NA EUV, the next-generation of extreme ultraviolet lithography with a higher numerical aperture. The company installed the first commercial High-NA EUV scanner from ASML in Oregon and plans to use both conventional EUV and High-NA EUV in the development and manufacturing of advanced nodes, including Intel 14A within that roadmap.
The advantage of High-NA EUV lies in patterning finer features with higher resolution and, in some cases, reducing the reliance on complex multi-patterning. However, each tool is extremely expensive, demands a learning curve, and requires adjustments in masks, metrology, design, and process control. Being first-to-market can confer advantages but also entails significant risk.
This helps to better understand the potential of 14A2. If Intel wants to capitalize on High-NA EUV and persuade external clients that its process offers a clear edge over TSMC and Samsung, it must demonstrate real density and efficiency improvements. An aggressive reduction of the M0 pitch and a hybrid power architecture could make the node more competitive but also increase complexity.
Modern foundries have become a trust-based business. Customers don’t choose just the most advanced node on paper. They consider process stability, manufacturing performance, EDA ecosystems, libraries, packaging, capacity, wafer costs, past performance, and risk of delays. Intel needs to build that trust beyond its own products.
What’s at stake for Intel Foundry
14A is more than a node—it’s a strategic test. Intel wants to prove it can once again compete in advanced manufacturing not only for its CPUs but also for high-end external clients. The market needs this, partly because TSMC concentrates too much demand for cutting-edge chips for AI, smartphones, HPC, and accelerators.
If Intel manages to make 14A and its variants attractive to real customers, it could become a serious alternative for companies seeking diversified manufacturing options. If not, the costs of developing such advanced nodes and purchasing costly equipment could become a burden difficult to justify.
The potential 14A2 architecture hints at a broader idea: chip scaling no longer depends on a single lever. Manufacturers combine gate-all-around transistors, back-side power delivery, narrower interconnects, High-NA EUV, new libraries, advanced packaging, and increasingly 3D integration. Those who better coordinate all these pieces will have the advantage.
The challenge is that each improvement carries its own cost. Increased density may lead to more resistance; greater integration complicates thermal management and yield; advanced lithography can raise wafer costs; automation tools demand further maturity. That’s why the race to 1.4 nm will not be just a headline battle but a comprehensive industrial test.
Intel appears to be preparing a more aggressive response to TSMC and Samsung. Still, it must first demonstrate the hardest part: that it can manufacture these processes at volume, with external customers, reasonable margins, and a credible schedule. In semiconductors, the roadmap opens the door; the factory decides who enters.
Frequently Asked Questions
What is Intel 14A2?
It’s a suspected evolution of the Intel 14A node mentioned in supply chain information. Intel has not officially announced it. The innovation would be in a dual-sided power delivery architecture.
What is PowerDirect?
It’s Intel’s technology for delivering power from the back side of the chip at the 14A node, an evolution of PowerVia designed to improve efficiency, reduce voltage drop, and free front interconnection resources.
Why is backside power delivery important?
Because it better separates power and signal lines. This can improve performance, efficiency, and density, especially in advanced nodes where interconnect space is very limited.
Does Intel 14A compete directly with TSMC A14 and Samsung SF1.4?
They target the same class of advanced 1.4 nm nodes, but they are not directly equivalent. Each manufacturer employs different technologies, design rules, timelines, and objectives.
Is the 14A2 timeline confirmed?
No. The available information suggests it’s a possibility under study. The only node Intel has publicly confirmed is 14A, which includes PowerDirect, RibbonFET 2, and use of High-NA EUV as part of its roadmap.
