TSMC Accelerates Glass Substrates for Next-Generation AI

TSMC is making moves in one of the less visible but most decisive layers of the race for AI chips: advanced packaging. The Taiwanese company, already under pressure from the huge demand for CoWoS for GPUs, ASICs, and AI accelerators, has reportedly started a collaboration with Ibiden and Innolux to validate the use of glass substrates in future generations of packaging, according to industry reports from Asian media.

This move points to a transition that the industry has been anticipating for some time. CoWoS, the packaging technology that has enabled the integration of large computing chips with HBM memory, will continue to be key in the coming years. However, the increasing size of packages, the need for more memory, power delivery challenges, and deformation issues are pushing TSMC and its supply chain toward a new stage: CoPoS, or Chip-on-Panel-on-Substrate.

This difference isn’t just terminological. CoPoS is part of panel-level packaging technologies, which seek to move from wafer-based processes to larger rectangular panels. The promise is to produce bigger, more efficient packages with better area utilization. In AI chips, where each generation adds more chiplets, more HBM, and more interconnects, this change could make the difference between scaling and hitting physical limits.

Why Glass Is Entering the Packaging Battle

Traditional organic substrates have gone a long way but are beginning to struggle with oversized packages. As package sizes grow, the risk of warpage—deformation of the entire assembly—increases. This deformation can impact layer bonding, solder joints, thermal reliability, and manufacturing performance.

Glass emerges as an alternative because it offers low deformation, lower thermal expansion, increased rigidity, and good electrical signal and power delivery properties. In theory, it can help build flatter, more stable packages—crucial when the main chip coexists with several taller stacks of HBM.

According to data cited by the supply chain, joint validation by TSMC, Ibiden, and Innolux has shown significant improvements over organic substrates: a 16% enhancement in the package deformation control indicator (COP), a 19% reduction in the effective coefficient of thermal expansion, and a 31% increase in the effective modulus, linked to structural rigidity.

The 85 × 110 mm figure is not minor. It typifies large AI GPU packages, where controlling flatness and preventing delamination are critical for performance, reliability, and manufacturing yield.

TSMC also noted that no cases of “SeWaRe,” or severe warpage, nor delamination, were detected during testing. In glass—a material where adhesion, fragility, and microcracks are real risks—this result indicates technical progress. While not yet ready for mass production, it suggests that glass has moved from exploratory to industrial validation stages.

CoWoS Continues, but CoPoS Is Taking Shape

This should not be interpreted as an immediate replacement of CoWoS. Current technology will remain vital for NVIDIA, AMD, Broadcom, Google, and other HPC and AI customers. TSMC continues expanding CoWoS capacity because demand far exceeds current supply.

What is changing is the direction for the next generation. CoPoS aims to overcome size, cost, and productivity barriers by using larger panels. If advanced packaging begins to be produced on panels rather than wafers, the industry could better utilize available area and support bigger packages that traditional processes cannot easily handle.

The transition will be slow. Industry sources suggest pilot lines in 2026 and potential volume production around 2028 or 2029. Some reports are even more conservative, indicating the commercial rollout could extend further. It makes sense: demonstrating that glass works in a sample is not enough. Mass manufacturing requires performance, cost control, thermal stability, and compatibility with real customers.

TSMC also highlighted that more research is needed regarding glass thickness and large-sized CoWoS layouts. Essentially, the material shows promise, but engineering details are still being finalized.

Ibiden and Innolux: Two Partners with Different Perspectives

Ibiden’s involvement is straightforward. The Japanese company is a key player in high-performance substrates for AI servers. In February 2026, it announced a plan to invest around 500 billion yen between 2026 and 2028 to expand high-performance IC substrate capacity aimed at AI servers and advanced data centers.

This investment aligns with pressures from clients like NVIDIA, AMD, and major AI chip designers. ABF substrates are already considered a bottleneck, and glass could become the next frontier if package sizes continue to grow.

Innolux offers a different perspective. As a display panel manufacturer, it has experience in large-format processes, glass handling, and manufacturing on rectangular surfaces. This expertise could be advantageous if advanced packaging moves toward panels instead of wafers. The display industry’s shift to advanced packaging isn’t automatic, but process skills are transferable.

The supply chain is rapidly reorganizing. Intel has been working on glass substrates for over a decade and operates pilot lines in Arizona. Samsung Electro-Mechanics, for its part, develops prototypes on its Sejong pilot line and, in 2025, signed an agreement with Sumitomo Chemical to create a joint venture focused on glass core materials, with mass production expected after 2027.

Competitive pressure on TSMC is clear. Intel is pushing advanced packaging and glass as differentiators. Samsung aims to get ahead in the new supply chain. While TSMC leads in CoWoS, it is eager not to fall behind in the next generation.

Main Challenge: Vias Through Glass

The main difficulty is not just manufacturing glass. The challenge lies in turning it into a functional substrate for advanced semiconductors. This requires thousands or even tens of thousands of conductive vias—known as TGV (Through Glass Via)—per substrate.

Glass is insulating, hard, and fragile. Drilling, metallizing, and filling it with copper without creating microcracks or defects is complex. Moreover, these vias must maintain reliability over thermal cycles, support current, preserve signal integrity, and coexist with ever-larger packages.

That’s why glass won’t be an immediate or universal solution. While it can improve many parameters, it also introduces new processes and demands additional equipment, materials, and quality controls. The industry must demonstrate that the benefits outweigh the added complexity.

In AI chips, the incentives are strong. NVIDIA’s GB200, GB300, and upcoming Rubin platforms increase pressure on packaging. More HBM, higher bandwidth, and greater power requirements mean larger and more stable packages. If the substrate doesn’t keep up, the ultimate limit will not just be lithography but also the system assembly capacity.

The Next AI War Is Beneath the Chip

This news confirms a recurring trend across the semiconductor ecosystem: AI is pushing the boundaries of layers that once received less public attention. HBM, CoWoS, ABF, interposers, glass substrates, TGV, power delivery, and cooling are all part of the same challenge. It’s not enough to design a more powerful chip if you can’t package, power, and manufacture it efficiently.

For TSMC, accelerating glass and CoPoS development is a way to safeguard its position in advanced packaging. For Ibiden, it’s an opportunity to establish itself as a critical supplier for the AI era. For Innolux, it could open a new market outside traditional display panels. For Intel and Samsung, it signals that the competitive landscape is shifting.

Major Challenge: Vias Through Glass

The main technical hurdle is not just making glass; it’s transforming it into a functional semiconductor substrate. This requires thousands of conductive vias—called TGV—that pass through the glass to enable electrical interconnects.

Glass is insulative, hard, and fragile. Drilling, metallizing, and filling it with copper without microcracks or reliability issues is challenging. These vias must support thermal cycles, carry current, and preserve signal quality in increasingly larger packages.

Therefore, glass will not be an immediate or universal solution. While it can significantly improve several parameters, it introduces new processes, equipment needs, and quality controls. The industry must validate that the benefits justify the added complexity.

In AI chips, the motivation is high. NVIDIA’s upcoming platforms, along with increasing design complexity, demand larger, more stable packages. If substrates can’t keep pace, the system’s overall performance ceiling will be limited not only by lithography but also by packaging capabilities.

The Next Frontier in AI: Beneath the Chips

This development confirms a broader industry trend: AI is pushing the frontiers of stacking, packaging, and interconnect technologies that once received less attention. Components like HBM, CoWoS, ABF, interposers, glass substrates, TGV, and cooling are all interconnected challenges. Improving just the chip design isn’t enough—you must also evolve packaging and assembly to keep pace.

For TSMC, advancing in glass and CoPoS measures is strategic to maintain leadership in next-gen packaging. For Ibiden, it’s a chance to reinforce its position as a vital supplier for AI infrastructure. For Innolux, it opens opportunities in new markets beyond display panels. For giants like Intel and Samsung, it signals ongoing shifts in the competitive landscape.

Glass has yet to fully take over. More validation, cost reduction, tooling, standards, and large-scale production are required. Nonetheless, it has officially entered the industrial race. As AI chips grow to sizes like 85 × 110 mm or larger, managing deformation is no longer just engineering detail—it’s a fundamental condition for enabling the next generation of accelerators.

FAQs

What is CoPoS?

CoPoS stands for Chip-on-Panel-on-Substrate. It is an advanced packaging technology that uses rectangular panels instead of relying solely on wafer-based processes.

Why are glass substrates of interest?

Because they can reduce package deformation, improve rigidity, better match thermal expansion with silicon, and enhance signal and power integrity in large AI chips.

Will glass immediately replace CoWoS?

No. CoWoS will remain critical in the coming years. Glass and CoPoS are more about enabling the next generation of advanced packaging.

What is the main technical challenge?

One of the biggest challenges is manufacturing TGV—Through Glass Vias—with good performance, no microcracks, and reliable thermal properties, especially at scale.

Source: Jukan on X