Intel is once again shining a spotlight on a technology many had considered obsolete: glass-core substrates applied to advanced packaging. At NEPCON Japan 2026, Intel Foundry showcased an implementation combining a ” thick core” of glass with EMIB (Embedded Multi-die Interconnect Bridge), a solution designed to integrate multiple chiplets within a single package and scale toward next-generation accelerators and HPC systems. This demonstration arrives in a context of high industrial sensitivity: data center module demand is pushing packaging toward larger sizes, more layers, and stricter mechanical tolerances, amid supply chain tensions affecting materials and capabilities.
A 78 mm × 77 mm Package and a 10-2-10 Stack for Connecting Chiplets
According to information published by Wccftech, based on material shown by Intel Foundry, the company has integrated a glass core within a 10-2-10 stacking architecture: ten redistribution layers (RDL) on the top, two layers of glass core, and ten bottom/build-up layers. The package size is around 78 mm × 77 mm, with an area Intel describes as equivalent to 2× the reticle size. It incorporates two EMIB bridges to connect multiple “compute dies” within the same set. The presentation (according to the source) suggests a clear target: “server-grade” products, effectively AI accelerators or HPC-oriented silicon where chiplet count and interconnection density influence final performance as much as the microarchitecture.
Why Glass Matters: Mechanical Stability and More “Wiring” in Less Space
Intel’s approach to glass isn’t new, but its public demonstration tied to EMIB packaging is. As early as 2023, Intel announced its roadmap to introduce glass substrates as a key lever for scaling complexity “inside the package” (more chiplets, interconnections, I/O) with an eye toward the second half of the decade. The technical rationale is consistent: glass can provide better dimensional stability, reduced warpage, and more dense wiring capabilities, enabling finer signal routing and a flatter, more controllable foundation for large multichip modules. In a market where each new generation of accelerators tends to grow in size, layers, and power consumption, mechanical considerations shift from manufacturing details to performance and reliability factors.
The Elephant in the Room: Large-Scale Packaging and Material Bottlenecks
Intel’s showcase coincides with an industry push toward ever larger modules with increased layers, especially in 2.5D and heterogeneous platforms focused on AI. In this leap, the “substrate” is no longer just a passive support but must withstand thermal stresses, mechanical forces, and electrical requirements (high frequencies, currents, more I/O) without compromising performance or yield.
Here enters the second thread of this story: the market’s dependence on materials like Ajinomoto Build-up Film (ABF). Sector analyses describe Ajinomoto as the dominant player in ABF for CPU/GPU substrates, with over 95% market share in this niche, and plans to expand capacity into 2030 in response to rising demand. For chipmakers and OSATs, ABF and related materials can become a bottleneck: it’s not enough to design the package; manufacturing at scale, reliably and with assured supply, is crucial.
ABF-GCP, T-glass, and the “Co-Design” of CTE: When Packaging Becomes Materials Engineering
Parallel to the push for glass as a core material, hybrid approaches like ABF-GCP (glass-reinforced composites with woven fabric and “primer” layers) are being explored to improve stability and absorb mechanical stresses. Industry literature highlights an increasingly common concept: the co-design of CTE (coefficient of thermal expansion) among stiffeners, resins, and stack layers. A solution that reduces warpage on one front can induce cracks on another if materials “pull” in different directions upon heating and cooling.
The impact is even felt in prices. In 2025, a 20% increase was reported for certain glass fiber products by Nittobo, interpreted as a sign of materials becoming more strategic for AI servers and advanced packaging. When substrate costs rise, the effect isn’t limited to manufacturing; it can influence schedules, margins, and overall platform availability.
What Intel Foundry Aims For: Packaging as a “New Revenue Frontier”
Intel’s implicit message is twofold: first, that glass is not just R&D but a practical way to support huge, dense packages; second, that advanced packaging (EMIB and beyond) is a competitive and commercial frontier itself. In a market where global capacity for advanced packaging is hotly contested, those able to industrialize reliable, repeatable solutions may gain influence beyond their own chip portfolio.
The key question now is the actual adoption rate. Showcasing an “industry first” at a tradeshow doesn’t mean supply chains are ready for mass volumes, but it does confirm that the race for AI accelerators has extended beyond lithography and transistors into materials, mechanics, and interconnects.
Frequently Asked Questions
What advantage does a glass-core substrate offer over an organic one for AI accelerators?
In very large, dense packages, glass can improve dimensional stability and help control warpage, facilitating finer interconnections and a flatter foundation for integrating multiple chiplets and HBM memories.
What is EMIB, and why is it relevant for “chiplet” architectures in HPC?
EMIB (Embedded Multi-die Interconnect Bridge) is a die-level interconnection technique that allows connecting multiple dies with high-density links without requiring a full interposer, enabling multi-chip configurations within a single package.
Why is Ajinomoto ABF so critical for advanced CPU and GPU packaging?
ABF is a key material for the build-up layers of high-density substrates. Its availability, cost, and technical evolution directly impact the industry’s ability to produce large, complex modules with acceptable yields.
How does rising fiber and glass fabric prices affect data center hardware supply?
If the costs of essential materials (specialized glass fibers, laminates, resins) increase, substrate costs rise, putting pressure on supply chains, and potentially impacting manufacturing schedules, final prices, and platform availability.
via: tspa semiconductor