SK hynix accelerates the race for the future NAND: 5-bit PLC, FeNAND 3D, and nearly production-ready CTI technology

NAND memory is once again at the center of the tech debate, driven by two relentless forces: the explosion of data associated with Artificial Intelligence and market pressure for more capacity per euro without compromising reliability. In this context, SK hynix has leveraged its recent presentations at technical forums to outline a roadmap with three very distinct—and interconnected—fronts: 5-bit-per-cell NAND (PLC) using a design called Multi-Site Cell (MSC), research into FeNAND 3D focused on compute-in-memory, and a more “industrial” process improvement called CTI, already demonstrated on a 176-layer node.

The common denominator is clear: as a single cell stores more bits, the margin for maneuver shrinks. The challenge is no longer just “storing more data,” but keeping it stable, reading quickly, and manufacturing cost-effectively.

From TLC and QLC to PLC: why 5 bits per cell is an awkward boundary

For years, moving from TLC (3 bits) to QLC (4 bits) has resulted in denser, more affordable SSDs—especially in cost-per-terabyte scenarios. The next step—PLC (5 bits per cell)—sounds enticing on paper, but introduces physical and statistical challenges: the more bits stored per cell, the more voltage levels must be distinguished accurately to identify the stored value.

To visualize, recall a basic NAND rule: the number of states grows as a power of 2.

This jump to 32 voltage levels (in PLC) explains why the industry has been cautious. Early prototypes and demonstrations exist, but large-scale industrialization demands extremely precise control over electrical variations, wear, and retention.

Multi-Site Cell: SK hynix’s shortcut to making PLC “manufacturable”

This is where SK hynix is trying to change the game with its Multi-Site Cell (MSC) approach. Described in their presentations and covered by industry media, the idea is to “divide” the cell’s behavior to drastically reduce the number of voltage thresholds that must be managed directly.

According to disclosed information, their approach would enable a design for 5 bits per cell that, instead of requiring 32 states, works with 6 base states. Through MSC, this results in 36 combinations (with margin), allowing the necessary states to be mapped. In essence: less analog complexity per unit, without sacrificing the final logical density.

The ambition doesn’t stop there. Under the same conceptual framework, SK hynix suggests MSC could enable, in the future, a 6-bit per cell (HLC) NAND with substantially fewer states than the traditional “64.” The company previously introduced MSC in 2022 as a way to push NAND beyond usual limits, but its current focus appears clear: making PLC viable before tackling even more extreme goals.

However, even with this promising approach, industry knows that the real bottleneck remains “cost-effectiveness.” Various reports indicate that SK hynix may have already manufactured functioning chips, but the remaining work involves proving cost efficiency, production yields, and stability to turn this into high-volume products.

FeNAND 3D: when memory aims to become a computational engine

The second front is less immediately consumer-facing but potentially disruptive for data centers: FeNAND (ferroelectric NAND), particularly in a 3D approach oriented toward Compute-In-Memory (CIM). CIM aims to reduce the energy and time costs of transferring data between memory and processor: if some operations are executed within or very close to the memory, bottlenecks and power consumption are minimized.

At IEDM, SK hynix highlighted results related to analog MAC (multiply-accumulate) operations and significant quantitative improvements over 2D matrices, including a 4,000x increase in CIM density, an accuracy of 87.8%, and a computational efficiency 1,000 times greater, measured as TOPS/mm² versus 2D implementations, according to their technical materials. Practically speaking, if these research lines mature, they could lead to flash memory that not only stores data but also helps perform calculations more energy-efficiently in specific workloads.

It’s important to note that this is still at the research and concept validation stage, not product announcement. Nonetheless, this aligns with a broader trend: the future of AI infrastructure depends not just on GPUs but also on memories and interconnects.

CTI: a “less sexy” but more practically aligned industrial improvement

The third pillar is likely the most immediate: Charge-Trap-Nitride Isolation (CTI). Unlike PLC or FeNAND, CTI doesn’t aim for a complete redesign of the cell, but to improve a critical aspect of NAND 3D: the distribution of threshold voltage (Vth) and charge retention. Both become more delicate as vertical scaling increases and margins shrink.

According to technical documentation related to IEDM 2025, SK hynix describes implementing CTI in a 176-layer NAND device with tangible metrics: an 11% reduction in read time (tR), a 6.9% narrower Vth distribution, and a 45% improvement in high-temperature retention after cycling, compared to conventional cells. Additionally, it’s suggested that from a variability and retention perspective, this technology could enable reducing layer pitch limits to around 4 nm (for Vth) and more than 10 nm (for retention).

In simple terms: CTI doesn’t promise an immediate “marketing leap” like PLC, but offers a more direct way to stabilize existing NAND technology, helping to sustain scaling without excessively compromising reliability.

What does all this mean for the market in 2026?

Combined, these three initiatives suggest that SK hynix aims to cover the entire spectrum:

• Extreme density (PLC with MSC) to push cost per GB lower.
• New architectures (FeNAND 3D) to meet AI’s energy demands.
• Industrial optimization (CTI) to support real scaling of current nodes.

The key question, as always, is timing. PLC has been appearing in lab headlines for years, and the market has learned to be cautious about timelines. Still, the fact that CTI is demonstrated on a 176-layer device with concrete improvement metrics suggests that at least this part of the project has a shorter path to production.

Frequently Asked Questions

When will commercial SSDs with 5-bit-per-cell PLC NAND become available, and what use cases will they suit?
The industry has shown prototypes and research lines, but the critical factor is whether they can be manufactured with sufficient performance and reliability. If they do emerge, they’ll likely first appear in capacity-oriented SSDs (mass storage, read-heavy workloads), rather than in high-performance, sustained-write drives.

What advantage does the Multi-Site Cell design offer over traditional PLC?
MSC aims to reduce the electrical complexity of distinguishing dozens of voltage levels—a core challenge for PLC. If the design can work with fewer “basic” states while still mapping the required values, it could improve manufacturability.

What is compute-in-memory (CIM), and why is FeNAND 3D interesting for AI?
CIM seeks to minimize data movement, one of the main sources of latency and power consumption. For AI workloads, which involve huge volumes of parameters and activations, this potential savings is especially attractive.

Will CTI improvements be noticeable in SSDs and data centers?
If Vth control, retention, and read times are effectively implemented into production, CTI could lead to more stable and efficient NAND, providing room to increase layer count and density without significantly sacrificing reliability.

via: computerbase.de and research.skhynix