JEDEC is finalizing a standard that could change how data centers supply memory for Artificial Intelligence. Under the name JESD328: LPDDR5/5X Small Outline Compression Attached Memory Module (SOCAMM2), the organization is advancing a low-profile modular format designed for AI servers and accelerated computing platforms. The promise combines high bandwidth, lower power consumption, and easier maintenance in densely packed chassis. Although the document hasn’t been published yet, the message is clear: bringing LPDDR5X energy efficiency—traditionally surface-mounted—to a replaceable module suitable for racks.
What is SOCAMM2 (and what does it solve)
SOCAMM2 is, in essence, LPDDR5/5X packaged in a compressed module with a low profile and an optimized mechanical outline for high-density boards and chassis in data centers. The key difference from traditional LPDDR (which is usually soldered) is that SOCAMM2 install as a module: it is serviceable, allows for field replacement, and includes a SPD device (Serial Presence Detect) for identification, configuration, and telemetry at the module level. For AI farms, this means reducing downtime and enhancing hardware lifecycle.
The approach tackles a recurring bottleneck: how to add bandwidth and capacity near AI CPUs and accelerators without increasing power draw and without sacrificing mounting density. SOCAMM2 proposes a middle ground between traditional DDR5 RDIMM, which is more flexible but less efficient, and HBM stacks, which are extremely fast but costly and complex.
Technical keys: speed, efficiency, and form factor
- LPDDR5X at full speed: the standard is designed to support up to 9.6 Gb/s per pin (9.6 Gbps), as long as the platform’s signal integrity permits. Practically, this enables high aggregate bandwidth with less energy per bit compared to conventional DDR alternatives.
- Low profile and high density: the compact outline eases short routing and allows more modules per board in dense servers.
- SPD and telemetry: the module self-identifies, exposes parameters, and enables qualification flows focused on field reliability—a critical aspect in enterprise environments.
- Scalability of capacity: although JEDEC hasn’t published final figures at this stage, the design supports a “scaling path” to cover large capacities needed for training and inference.
The focus is on memory subsystem energy efficiency. LPDDR5/5X operates at low-voltage modes that, in large-scale deployments, reduce watts and cooling needs compared to similar setups with RDIMM/LRDIMM. In a modern data center, every watt saved in memory translates to less heat to dissipate, less airflow to move, or less water needed for cooling.
Why SOCAMM2 fits the AI era
The rise of generative AI has prompted manufacturers to rethink memory hierarchies. Alongside HBM that “embraces” GPUs, AI server CPUs and accelerated platforms require system memory with high throughput without impacting the PUE of the data center. That’s where SOCAMM2 fits in:
- Bandwidth per watt: LPDDR5X offers more GB/s per watt than registered DDR5, useful for data ETL, model serving, and pipelines where CPUs or DPU/SmartNICs heavily rely on memory.
- Density and maintainability: the low profile simplifies layouts and leaves space for more GPUs, networks, or radiators. Its serviceable nature reduces friction compared to soldered LPDDR.
- Complement to HBM: not intended to replace HBM in GPUs but to support systems with modular LPDDR where cost and efficiency matter, and possibly in accelerators that prefer LPDDR modules.
Differences with CAMM2 “laptop” version and original SOCAMM
It’s important not to mix abbreviations. CAMM2, ratified by JEDEC for PCs, already explored advantages of compression and low profile versus SO-DIMM in portables and workstations. SOCAMM (Small Outline CAMM) later emerged as a variant aimed at servers/AI, based on LPDDR5X to maximize bandwidth and efficiency.
SOCAMM2 takes that concept and brings it to JEDEC standards for data centers, refining form, signaling, SPD, and telemetry with an emphasis on reliability and serviceability. The goal: shift from proprietary or limited-adoption designs to an open standard that expands module availability and simplifies integration for OEMs and operators.
What it means for manufacturers and operators
- For OEMs/ODMs: a common format reduces the need for custom boards and firmware. Interoperability among DRAM providers (Micron, Samsung, SK hynix, etc.) and connector/board manufacturers accelerates validation and shortens time-to-market.
- For system integrators and cloud providers: module telemetry, clear identification, and reliability qualification are key advantages in large-scale operations. Less “strange” inventory, more guided substitutions, and fleet control.
- For TCO: the equation combines sustained performance per watt and mechanical simplification, with the yet-to-be-determined costs of the emerging ecosystem. The potential gains lie in energy and cooling, two areas that keep increasing in AI farms.
What still remains unknown (and why it’s normal)
JEDEC cautions that standards may evolve during development. Until JESD328 is finalized, details on electric specifications, pin maps, thermal limits, definitive SPD profiles, and compatibility matrices are yet to be determined. There’s also no official capacity table per module, though the design suggests scalability upwards to meet training and inference needs.
How to interpret the figures and nuances
- “Up to 9.6 Gb/s per pin” means that LPDDR5X’s upper limit can be utilized if the board and connector design ensure signal integrity. In dense servers, routing and reference returns matter just as much as the DRAM itself.
- SPD/telemetry: not just “auto-discovery,” but also enables status readings and error logs at the module level, useful for predictive maintenance and SLA management.
- “Low profile” isn’t just aesthetic—it reduces height and airflow shadows, freeing space for other critical AI node functions.
Market context: why now
This advancement comes as HBM dominates the discourse but remains limited by availability and cost. Meanwhile, DDR5 RDIMM has increased in speed and timing, but at the expense of wattage and heat in extreme racks. In this landscape, modular LPDDR5X can be the “system memory” that AI CPUs, DPUs, FPGAs, and accelerators need—without HBM. If the standard takes hold, multiple players will be able to offer SOCAMM2 modules and compatible boards with more predictable upgrade cycles.
What to watch in the coming months
- Standard publication: the shift from “almost ready” to the formal JESD328 document will set the guidelines for firmware, BIOS/UEFI, SPD, and connectors.
- Initial platforms: motherboards or servers explicitly announcing compatibility with SOCAMM2.
- Offers from the big three (Micron, Samsung, SK hynix): densities, binnings, and profiles tailored for data centers.
- Validation ecosystem: tools for burn-in, telemetry, and qualification to translate the standard into 24/7 operation.
Conclusion: efficiency and service—two critical factors in AI
SOCAMM2 doesn’t aim for flashy headlines; it seeks to fit into the rack environment where today everything is about energy, density, and operation. If JEDEC finalizes the standard and industry adopts it, AI servers will gain a modular memory option, fast, watt-efficient, with telemetry and serviceability that critical systems demand. It does not displace HBM; it complements it. And compared to registered DDR5, it offers a more efficient alternative when the challenge isn’t just “more GB/s,” but more GB/s per watt and per cubic meter of airflow.
Frequently Asked Questions
How does SOCAMM2 differ from CAMM2 (laptop) and the original SOCAMM?
CAMM2 was designed for PCs as a replacement for SO-DIMM, featuring compressed, low-profile modules. SOCAMM is the adaptation for servers/AI using LPDDR5/5X to maximize efficiency. SOCAMM2 is the JEDEC-standard evolution for data centers, focusing on telemetry, reliability, and high bandwidth.
Does SOCAMM2 compete with HBM on GPUs?
Not directly. HBM will remain where extreme bandwidth close to the die is needed. SOCAMM2 targets system memory for AI CPUs, DPU, accelerators, in scenarios where GB/s per watt and serviceability are more critical than peak bandwidth.
What speeds and power consumptions are expected?
JEDEC’s technical sheet anticipates up to 9.6 Gb/s per pin for LPDDR5X, conditioned on signal integrity. The power savings come from the low-power nature of LPDDR5/5X compared to DDR5, reducing energy dissipation and thermal load in dense racks.
When will it be available, and how will it be integrated?
JEDEC indicates the standard is almost finalized. After publication, qualified boards and modules will follow. Integration will involve firmware/BIOS support, SPD/telemetry, specific connectors, and signal integrity validation at 9.6 Gb/s per pin.
via: jedec.org