The RISC-V community is arriving at its annual flagship event with a bold headline: chips based on the open standard have surpassed 25% market penetration, a milestone that advances several years beyond analysts’ forecasts. According to a report shared by RISC-V International on LinkedIn and to be detailed by SHD Group at the RISC-V Summit North America (October 21–23), this new projection raises the horizon to more than 20 billion units by 2031 and places RISC-V IP revenue at > $2 billion before 2031 if the current growth rate persists.
It’s not just an increase in numbers. The organization attributes part of this momentum to Edge AI use cases — that is, artificial intelligence at the edge — from gateways and smart sensors to local nodes that filter, infer, and act without sending all traffic to the cloud. This, combined with the rapid iteration cycles enabled by an open, royalty-free ISA, is accelerating adoption in IoT, automotive, industrial, wireless, specialized data centers, and even space, according to the foundation.
Why it matters: open ISA as a lever for cost and sovereignty
The defining feature of RISC-V is its open standard: any company or group can use, implement, and extend the instruction set without paying licensing fees or signing contracts with a governing body. Practically:
- Cost and freedom: designers and foundries save royalties and gain margin opportunities for customization in microarchitectures.
- Community speed: hundreds of engineers and companies contribute to new extensions (vector, cryptographic, cache management, security), with public roadmaps and peer review.
- Technical sovereignty: governments and large manufacturers see RISC-V as a “neutral” foundation for building sovereign computing stacks without contractual dependence on a single vendor.
In contrast, Arm — the historic rival in the RISC world — monetizes through ISA licenses and pre-designed cores, offering close support and a highly polished ecosystem of IP, tools, and software, in exchange for royalties based on volume. The RISC-V moment doesn’t eliminate Arm’s position but expands the competitive landscape: more discrete design wins, more customized silicon, and new categories that previously didn’t justify licensing costs.
The numbers: from 25% today to 20B+ units and > $2B in IP revenues
- 25% market share: RISC-V International itself projected that a quarter of silicon incorporates RISC-V cores (often as coprocessors or embedded controllers within larger SoCs).
- 20 billion+ chips by 2031: the new SHD Group forecast improves upon Omdia’s 2024 projection (which estimated the 25% share for 2030 with 17 billion shipments), raising the bar to 21B+ for 2031.
- > $2 billion in IP: aggregated revenues from licenses for commercial cores, services, tools, and complementary blocks around the open ISA (though the ISA itself is free, the business is in optimized IP, verification, physical IP, toolchains, and support).
The full picture will be unveiled in the keynote at the Summit in Santa Clara, with attendees including Google, AWS, and NASA, amidst a dynamic backdrop: Meta (Facebook) has stepped up its interest in RISC-V — including the acquisition of the GPU startup Rivos — to advance in RISC-V-based AI accelerators.
Where growth is happening: from microcontrollers to edge AI
- IoT and embedded
The “natural playground”. Meters, sensors, wearables, PMIC controllers, always-on… billions of microcontrollers where cost and efficiency outweigh peak performance. RISC-V is already a de facto standard in many peripheral designs within SoCs. - Edge AI
Nodes that preprocess audio/video, run compact models (person/object detection, anomaly detection), federate learning, or orchestrate local devices. Here, vector extensions and NPU blocks combined with RISC-V control are key. - Automotive
Control domains, safety islands, and MCUs for critical zones (ASIL). Medium term, roadmaps point towards domain-specific SoCs with heterogeneity: RISC-V CPU + accelerators. - Infrastructure and specialized data centers
Managing smart NICs (DPUs/IPUs), storage offload, SmartNICs, power management, and BMCs…Unseen but impactful segments of data centers that add real volumes. - Aerospace and defense
Growing interest in open ISA + certifiability + verified supply chain for long-life-cycle missions and systems.
What the leap is enabling (beyond the ISA)
- High-performance commercial cores: IP vendors are offering scalable RISC-V CPUs with wide pipelines, out-of-order support, and SMP/NUMA, bringing RISC-V closer to general-purpose Linux and rich applications.
- Vector extensions and custom ISA: the standard allows extensions without breaking core compatibility, enabling differentiation (e.g., crypto, vision, bit manipulation) while maintaining a common base.
- Tools and toolchains: mature GCC/LLVM, debuggers, simulators; and a professional verification ecosystem (UVM, formal, coverage) that reduces tape-out risk.
- Operating systems and middleware layers: Linux, Zephyr, FreeRTOS, and already stable RISC-V stacks; lightweight containers and support for modern runtimes.
Pending challenges: software, certifications, and fragmentation
Not everything is smooth sailing. To keep the growth curve, the community must resolve or mitigate:
- High-performance software stacks: optimized schedulers, libraries, tuning for HPC/AI, hypervisor support for enterprise, and broader ISV ecosystems.
- Certification for safety in automotive/industrial sectors: complete ASIL/IEC chains, tool qualification, and audit-ready documentation.
- Fragmentation risk from proprietary extensions: the value of RISC-V lies in the commons; too many incompatible variants erode its appeal.
- Verification talent: designing a core is “just the beginning”; enterprise-scale verification—timelines, costs, methodologies—remains a barrier for many newcomers.
The good news is that the Summit and working groups — both technical, industry, and security-focused — are directly addressing these layers, with increasingly convergent specifications and more demanding compliance tests.
An existential threat to Arm or cohabitation?
In the next five years, the most likely scenario is competitive coexistence:
- Arm will maintain dominance in mobile and high-performance client devices, and strengthen its role in automotive autonomy and general-purpose servers, supported by a deep software ecosystem and verified end-to-end IP.
- RISC-V will continue expanding from embedded into Edge AI and specialized domains, with strategic entries into client and data center where ISA customization provides material advantages (power per watt, latency, TCO).
If the projection of >20 billion units and > $2 billion in IP revenue bears out, market segments will likely be delineated by application lines, not by a clear winner. For users and system integrators, more options often translates into better ROI and greater design sovereignty.
What to expect from RISC-V Summit North America
Apart from the formal quota announcement, the agenda in Santa Clara promises:
- Edge AI use cases: keynotes and demos on local inference, sensor fusion, and federated learning with RISC-V + NPU/DSP.
- Tooling and security: compilers, debugging, secure boot, TEE, and new cryptographic extensions.
- Cloud ecosystem: contributions from Google and AWS on toolchains, CI/CD, and ecosystem enablement.
- Aerospace/defense: experiences from NASA and contractors regarding reliability, radiation, and certification.
The overarching industry sentiment is that RISC-V has shifted from “promise” to “deployment” across multiple verticals, and that the 2025–2027 period will be critical for seeing more complex SoCs and volume products with the open ISA at their core functions, not just peripherals.
Frequently Asked Questions
How can RISC-V generate $2 billion in revenue if the ISA is free?
The ISA is open and royalty-free, but revenues come from commercial IP (cores, subsystems), services, verification, tools, physical IP, and support. This mirrors the open software model: value is created in products and services built around the standard.
Where will we first see powerful RISC-V implementations?
Primarily in Edge AI and specialized domains (DPU, storage offload, domain automotive). General-purpose PC/server markets will follow gradually as OoO cores and software ecosystems mature.
Will RISC-V replace Arm?
More likely, they will coexist. Arm retains advantages in ecosystem, ISV, and proven IP. RISC-V is gaining ground where cost, customization, and sovereignty matter more, and where extensions offer clear advantages.
What risks does RISC-V face?
Fragmentation from incompatible extensions, middleware/ISV performance gaps, and the challenge of industrializing large-scale verification. Its management will determine whether the 25% growth rate remains sustainable.
Sources: LinkedIn and Linux Foundation