The craze for AI and the push of high-performance computing (HPC) have pushed TSMC to the limits of their capacity. Market reports indicate that their 3 nm (N3) and 5 nm (N5) nodes are almost fully booked next year, with demand concentrated on mobile devices and HPC/AI — from Apple to NVIDIA, AMD, Qualcomm, and MediaTek. Access to advanced wafers is becoming more complicated, and prices could be strained.
The bottleneck shifts to the “front-end”: N3 and N5 with no gaps
In 2024, saturation was already observed in advanced packaging (CoWoS/SoIC), driven by the surge in AI accelerators. Now, in addition to the back-end bottleneck, there is an almost full utilization in the front-end (lithography at 3 nm and 5 nm), causing wafer and packaging processes to tighten simultaneously. The result is longer lead times, less elasticity for peaks, and probable price increases in these star nodes.
Already in mass production are 3 nm products such as Apple, MediaTek, and Qualcomm mobile SoCs and it will serve as the foundation for upcoming M-series chips for Macs. Meanwhile, the latest GPUs and AI accelerators — like NVIDIA’s Rubin or AMD’s Instinct — are migrating to 3 nm nodes with very high-density packaging (HBM and advanced interposers). The simultaneous demand from mobile and AI puts a strain on a finite resource: latest-generation EUV/DUV lithography hours.
Apple, a major anchor… also in 2 nm
If 3 nm is nearing “fully booked”, 2 nm (N2) shows early signs of capacity reservations by Apple through 2026, as a precaution to ensure supply during the transition to GAA nanosheets. While initial volumes of N2 will grow gradually, reserving “slots” confirms a key fact: cutting-edge silicon is planned years in advance, and large clients secure manufacturing windows before the flood of orders hits.
U.S. accelerates: Arizona and the “friend-shoring” of leading-edge manufacturing
Geographic diversification is part of the strategy. TSMC Arizona launched 4 nm capacity in early 2025, with plans for 3 nm and a second fab targeting 2 nm by the end of the decade, supported by incentives from the CHIPS Act and anchor contracts. Washington’s goal is to reduce dependence on Taiwan for cutting-edge technology and
shorten critical AI supply chains. However, scaling up N3/N2 capacity is costly and gradual: while N3 in Arizona gains ground, most volume will still stay in Hsinchu/Tainan for years.
Japan joins with Rapidus: aiming for 2 nm by 2027
The Rapidus consortium — with government support and tech alliances — aims to mass produce 2 nm chips in 2027 from Hokkaido. Although it doesn’t yet rival TSMC in scale, it offers an alternative supply option for high-end nodes in the medium term. Japan seeks to reintegrate itself into the advanced manufacturing elite and complement the relocations promoted by the U.S. and EU.
Why now: the double wave of mobile + AI
- AI/HPC: cloud providers and large platforms consume accelerators across generations (Blackwell→Rubin), with increasing needs for HBM and CoWoS.
- Premium Mobile: Apple, Qualcomm, and MediaTek are rapidly shifting to 3 nm for energy efficiency and performance; the push of AI phones/PCs adds volume.
- Packaging: even if lithography capacity is available, bottlenecks emerge without enough CoWoS/SoIC. TSMC is expanding lines, but demand is outpacing.
Chips as scarce resources: market effects
- Lead times and prices: with N3/N5 close to capacity, foundries’ pricing power shifts; customers with long-term agreements and prepayments will be better positioned, while those buying at spot will suffer.
- Mix prioritization: HPC/AI and high-end mobile are displacing lower-margin categories. Expect more N5→N3 migrations and internal transfer shifts to maximize revenue per mm².
- Multi-foundry strategies: in the short term, the leading edge remains concentrated at TSMC; in the medium term, Samsung Foundry and Rapidus could offer relief if performance and ecosystem improve.
What large clients can do
- Secure packaging: reserving CoWoS/SoIC is as critical as securing lithography slots; many delays in 2024-2025 are more due to packaging issues than wafers.
- Prepayments & LTAs: making down payments and establishing multi-year agreements helps secure capacity and reduce price volatility.
- Portable designs: planning variants with N5/N4/N3 reduces risk if a node becomes saturated or if yield forces aggressive binning.
- HBM planning: memory is another bottleneck (HBM3E→HBM4); coordination with SK hynix, Samsung, and Micron and interposers is vital to avoid delaying launches.
Role of regulators: economic security and “friend-shoring”
The U.S. is pushing to increase manufacturing domestically — Arizona already produces at 4 nm — and aims for 2 nm by the late decade. The goal is to go from nearly 0% of leading-edge logic in 2023 to ~20% in 2030. Europe is leveraging subsidies and alliances (manufacturing and packaging), and Japan is accelerating with Rapidus. These are very costly, long-term bets, but geographical diversification of tech leadership is now a state policy.
The 2026 outlook: more supply, but tension persists
By 2026, expect more CoWoS capacity, mature 3 nm (N3E/N3P), and some initial significant volumes of 2 nm (especially for Apple). Yet, the AI appetite remains strong: if new accelerators maintain the demand curve, relative shortages may persist despite capacity expansions. The cycles of enterprise AI (training & serving), PCs with NPU, and AI-first mobiles will raise the floor of advanced wafer consumption.
Key points to understand the moment
- There’s no single bottleneck: EUV, yields, CoWoS, HBM, and interconnect may all influence the final delivery rate.
- Asymmetry is structural: a few players dominate the leading edge; changing that requires years and decades of investment.
- Value per wafer rules: with demand exceeding supply, foundries prioritize high-margin mixes like AI and flagship mobiles.
Frequently Asked Questions
Is it confirmed that TSMC will have no gaps in 3 nm and 5 nm capacity in 2026?
Market reports point to almost full capacity in N3 and strong pressure in N5, with queues extending into 2026. No official statement is definitive yet, but signs are consistent with the saturation observed in advanced packaging.
Will wafer process prices rise at N3/N5?
It’s plausible, especially in a demand exceeds capacity environment and during capacity expansions (like Arizona). Past experiences with N3 have already shown upward pressures when shortages intensified.
Can Apple “block” 2 nm and exclude others?
As an anchor customer, Apple can reserve a large portion of initial N2 capacity. This limits availability to others at launch, although overall capacity will grow through 2026-2027.
When will real relief from shortages happen?
As N3/N3E matures, N2 launches, and CoWoS ramps up, supply should improve. Still, if AI continues to grow at the investment rate, demand may absorb additional supply until 2026-2027.
via: wccftech