SiFive has announced its second generation of IP Intelligence for RISC-V processors, a family aimed at accelerating artificial intelligence workloads from the far edge and IoT to the data center. The lineup includes five products: the new X160 Gen 2 and X180 Gen 2, and the revisions X280 Gen 2, X390 Gen 2, and XM Gen 2, with improvements in scalar, vector, and, in the case of XM, matrix compute. Licensing is available immediately, and the first silicon is expected in Q2 2026.
The company frames the announcement during a period of strong demand: according to data cited by SiFive, AI workloads will grow at least 20% across all technology environments, with 78% at the edge AI. The product strategy reinforces the idea that RISC-V is a credible alternative for custom silicon, with configurations scaling from narrow vector microcontrollers to matrix clusters for HPC/AI.
What’s new: family, positioning, and use cases
- X160 Gen 2 and X180 Gen 2 (X100 series): geared toward far edge and low-power IoT with limited area, featuring vectorization for local inferences and accelerator control functions. Target sectors include: automotive, autonomous robotics, industrial, and smart IoT.
- X280 Gen 2 and X390 Gen 2: evolution of the X200/X300 series with wider vectors, new data types, and bandwidth improvements; the X390 doubles vector length and adds dual vector ALUs to boost performance。
- XM Gen 2: scalable matrix core designed for deep networks and transformers, configured as a high-throughput engine and aimed at multi-instance on the same chip.
All X-Series cores can function as Accelerator Control Units (ACUs): managing and assisting external accelerators via SSCI (SiFive Scalar Coprocessor Interface) and VCIX (Vector Coprocessor Interface Extension), simplifying software orchestration and enabling clients to focus innovation on the data pipeline.
Architecture: vector + matrix and AI-optimized memory
1) Memory latency tolerance
One of the most interesting innovations is the Memory Latency Tolerance scheme. The scalar core issues vector instructions to a Vector Command Queue (VCQ); when a vector load occurs, the address is immediately sent to the memory subsystem. The response is stored in a configurable Vector Load Data Queue (VLDQ). When the load exits the VCQ, data is already waiting, enabling a “load-to-use” within a cycle and preventing pipeline bubbles. In four-core configurations, SiFive reports up to 1,024 pending requests, compared to 128 in a recent Xeon.
2) More efficient cache hierarchy
The second gen shifts from an inclusive to a non-inclusive hierarchy, with optional shared L2 and better effective utilization of on-chip memory area. As a result: roughly 1.5× useful capacity compared to Gen 1, with about 60% of the previous area, freeing space for more compute or buffers.
3) Hardware-accelerated exponentials
Beyond the traditional MAC domain, SiFive introduces a hardware pipelined exponential unit. Operations like softmax—which can account for over 50% of residual cycles after accelerating MACs in BERT-Large—drop from 22→15 cycles with software optimization to about 5 cycles total thanks to this unit.
Integration flexibility: from edge to data center
The Intelligence Gen 2 family emphasizes modularity:
- Adjustable vectors to match area and power budgets.
- XM as a scalable, clusterable matrix block; the current runtime distributes loads among multiple XMs within the same chip, and future plans include IPC libraries for scaling beyond a single die.
- ACU mode across all X-Series to interface with third-party or client accelerators via SSCI/VCIX, reducing bus traffic and improving coupling for pre/post-processing tasks.
This approach aligns with the trend of hyperscalers and large service providers designing their own chips: many architectures still deploy Arm cores in applications but incorporate SiFive XM cores or proprietary matrices governed by RISC-V control from SiFive.
Software and standards: RVA23, RVV 1.0, and mature stack
The Gen 2 includes support for recent profiles like RVA23 and expands RVV 1.0 pathways with new data types, more cache options, and I/O ports. SiFive’s software stack — built over four+ years of investing in AI on RISC-V — aims at a unified stack capable of serving edge and data center needs.
Market traction and timeline
SiFive reports early adoption of the new X100 by two Tier 1 US semiconductor companies, with use cases ranging from acting as an ACU with a matrix engine to functioning as an autonomous vector accelerator. The IP license for the five IPs is already available, with first silicon expected in Q2 2026. The company will showcase the family at the AI Infrastructure Summit (Santa Clara, September 9–11, booth #908).
Why it matters (and for whom)
- For silicon architects: the vector + matrix combination under an open ISA and the ACU mode simplify heterogeneous SoCs, where memory control is as crucial as TOPS.
- For MLOps/infrastructure teams: XMs for batch workloads and X-Series for pre/post-processing in the same die allow more compact pipelines with fewer latency hops.
- For the edge: X160/X180 bring useful AI features (vectors, hardware exponentials, contained latencies) to tight thermal budgets, enabling deterministic control and on-device AI with low power consumption.
Quick comparison
| Component | Main role | Compute | Typical use cases |
|---|---|---|---|
| X160 Gen 2 | Highly constrained edge | Scalar + narrow vector | IoT, sensors, accelerator control |
| X180 Gen 2 | Efficient edge/industrial | Scalar + vector | Robotics, automotive, lightweight vision |
| X280 Gen 2 | Edge/Infra performance | Scalar + enhanced vector | Mobile AI/infra, advanced DSP |
| X390 Gen 2 | High-performance vector | Scalar + wide vector | Pre/post-processing for LLM/CNN |
| XM Gen 2 | Matrix acceleration | Matrix + vector | Large language models, high-density inference in data centers |
Conclusion
SiFive’s Intelligence Gen 2 represents a significant step towards industrializing RISC-V in AI: it combines mature vectorization, a scalable matrix engine, optimized memory and non-linear accelerators, and a control mode that reduces integration friction. If clients materialize designs in 2026 and the software stack keeps pace, this approach offers a flexible, more efficient pathway to bring AI from device to data center under a single ISA.
FAQs
What is the key difference between Gen 2 and the previous generation?
Three pillars: memory latency tolerance, non-inclusive hierarchy with better cache utilization, and hardware accelerators for softmax and other non-linear functions.
Can I combine X-Series vector cores with custom matrix engines?
Yes. All X-Series can serve as ACUs via SSCI/VCIX, coordinating external accelerators and simplifying the software stack.
When will hardware be commercially available?
The IP is available for licensing today; SiFive expects the first silicon in Q2 2026.
Where can I find demos and technical documentation?
SiFive will showcase the family at the AI Infrastructure Summit (Santa Clara, September 9–11) and provides public product briefs for each series on their website.
via: SiFive