Socionext, a Japanese company specializing in System-on-Chip (SoC), has taken a significant step forward in advanced packaging solutions by announcing support for 3DIC and 5.5D in its service portfolio. This innovation, aimed at both consumer sectors and applications in artificial intelligence (AI) and High Performance Computing (HPC), seeks to meet the growing demands for density, energy efficiency, and performance required by the new era of semiconductors.
A milestone with TSMC: stacked 3D chips
As part of this advancement, the company has successfully completed the design (tape-out) of a device in collaboration with TSMC, using the SoIC-X 3D stacking technology. This configuration combines a 3nm node compute chip with a 5nm I/O chip in a face-to-face (F2F) arrangement.
This approach drastically reduces the interconnection distance between chips, resulting in:
- Lower signal latency.
- Higher effective bandwidth.
- Reduced power consumption, thanks to shorter, lower-impedance connections.
Compared to traditional 2D or even 2.5D designs, the leap to 3DIC represents a structural shift in how systems are built within a single package.
From 2.5D to 3DIC: moving toward heterogeneous integration
Socionext’s experience with 2.5D packaging allows it to apply proven methodologies to vertical chip integration, paving the way for what the industry calls heterogeneous integration:
- Multiple technology nodes (3 nm, 5 nm, 7 nm) can coexist within a single package, enabling each component to be manufactured using the most efficient process for cost and performance.
- Diverse functionalities (logic, memory, interfaces) are integrated into one device.
- Higher density in smaller space, essential for increasingly compact mobile and consumer electronic devices.
The intermediate step: 5.5D packaging
In addition to 3DIC, Socionext is also exploring 5.5D, an intermediate concept that combines the benefits of 2.5D interconnects with vertical stacking techniques. This hybrid model offers greater flexibility to integrate different chiplets into optimized configurations for a range of applications, from smartphones to AI supercomputers.
Implications for AI, HPC, and consumer electronics
The progress comes at a critical time when Moore’s Law limitations are prompting the industry toward new architectures and packaging methods. With these technologies, Socionext aims to serve several sectors:
- Artificial Intelligence and Data Centers: Processors with enhanced parallel computing capacity, lower latency, and improved energy efficiency for training and executing large-scale AI models.
- High Performance Computing (HPC): Greater integration density allowing acceleration of scientific simulations, big data analysis, and critical industrial applications.
- Consumer Devices: Smartphones, wearables, and mixed reality equipment demanding more processing power in smaller spaces without sacrificing battery life.
Statements and future outlook
“Socionext’s extensive expertise in SoC design, combined with our collaboration with TSMC, places us at the forefront of developing next-generation chips,” said Rajinder Cheema, CTO and Executive Vice President of Socionext. “This milestone reflects our commitment to cutting-edge solutions that address our clients’ evolving needs.”
Context: the new global landscape of semiconductors
Socionext’s announcement adds to the race for advanced packaging, an area where giants like TSMC, Samsung, and Intel are investing billions. Amidst the slowdown of traditional scaling, the industry sees vertical and heterogeneous integration as key to continuing performance and efficiency improvements.
In Japan, such initiatives align with efforts toward technological sovereignty, involving companies like Rapidus and government-backed consortia.
Conclusion
Socionext’s move toward 3DIC and 5.5D packaging demonstrates how semiconductor companies are redefining innovation beyond transistors. With a focus on heterogeneous integration and energy efficiency, the Japanese firm is positioning itself to play a central role over the next decade, where AI, HPC, and consumer electronics converge in increasingly compact and powerful devices.
Frequently Asked Questions (FAQ)
1. What’s the difference between 2.5D, 3DIC, and 5.5D?
2.5D uses interposers to connect chips in a plane, 3DIC stacks chips vertically to reduce latency and power, and 5.5D combines both approaches for greater flexibility.
2. Why is heterogeneous integration important?
It allows different technology nodes and functions (logic, memory, interfaces) to be integrated into a single package, optimizing cost and performance.
3. What role does TSMC play in Socionext’s development?
TSMC provides its SoIC-X stacking technology, enabling the combination of chips fabricated in different processes (3 nm and 5 nm) with more efficient interconnections.
4. What impact will this have on consumers?
Devices will become smaller, with longer battery life, better performance, and native AI capabilities.
via: prnewswire